Renesas RL78 Series User Manual page 554

RL78/G1D
EXCn
0
1
Condition for clearing (EXCn = 0)
● When a start condition is detected
● When a stop condition is detected
● Cleared by LRELn = 1 (exit from communications)
● When the IICEn bit changes from 1 to 0 (operation
stop)
● Reset
COIn
0
1
Condition for clearing (COIn = 0)
● When a start condition is detected
● When a stop condition is detected
● Cleared by LRELn = 1 (exit from communications)
● When the IICEn bit changes from 1 to 0 (operation
stop)
● Reset
TRCn
0
1
Condition for clearing (TRCn = 0)
<Both master and slave>
● When a stop condition is detected
● Cleared by LRELn = 1 (exit from communications)
● When the IICEn bit changes from 1 to 0 (operation
stop)
● Cleared by WRELn = 1
● When the ALDn bit changes from 0 to 1 (arbitration
loss)
● Reset
● When not used for communication (MSTSn, EXCn, COIn
= 0)
<Master>
● When "1" is output to the first byte's LSB (transfer
direction specification bit)
<Slave>
● When a start condition is detected
● When "0" is input to the first byte's LSB (transfer
direction specification bit)
Note When bit 3 (TRCn) of the IICA status register n (IICSn) is set to 1 (transmission status), bit 5
(WRELn) of IICA control register n0 (IICCTLn0) is set to 1 during the ninth clock and wait is
canceled, after which the TRCn bit is cleared (reception status) and the SDAAn line is set to high
impedance. Release the wait performed while the TRCn bit is 1 (transmission status) by writing to
the IICA shift register n.
Remarks 1.
R01UH0515EJ0120 Rev.1.20
Dec 16, 2016
Figure 14-7. Format of IICA Status Register n (IICSn) (2/3)
Extension code was not received.
Extension code was received.
Addresses do not match.
Addresses match.
Receive status (other than transmit status). The SDAAn line is set for high impedance.
Transmit status. The value in the SOn latch is enabled for output to the SDAAn line (valid starting at
the falling edge of the first byte's ninth clock).
Note
(wait cancel)
LRELn: Bit 6 of IICA control register n0 (IICCTLn0)
IICEn: Bit 7 of IICA control register n0 (IICCTLn0)
2. n = 0
CHAPTER 14 SERIAL INTERFACE IICA
Detection of extension code reception
Condition for setting (EXCn = 1)
● When the higher four bits of the received address
data is either "0000" or "1111" (set at the rising edge
of the eighth clock).
Detection of matching addresses
Condition for setting (COIn = 1)
● When the received address matches the local
address (slave address register n (SVAn))
(set at the rising edge of the eighth clock).
Detection of transmit/receive status
Condition for setting (TRCn = 1)
<Master>
● When a start condition is generated
● When 0 (master transmission) is output to the LSB
(transfer direction specification bit) of the first byte
(during address transfer)
<Slave>
● When 1 (slave transmission) is input to the LSB
(transfer direction specification bit) of the first byte
from the master (during address transfer)
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