Renesas RL78 Series User Manual page 401

16-bit single-chip microcontrollers

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Table of Contents

Address: F0110H, F0111H (SMR00) to F0116H, F0117H (SMR03),

F0150H, F0151H (SMR10), F0152H, F0153H (SMR11)

Falling edge is detected as the start bit.

The input communication data is captured as is.

Rising edge is detected as the start bit.

The input communication data is inverted and captured.

Transfer end interrupt

Buffer empty interrupt

(Occurs when data is transferred from the SDRmn register to the shift register.)

For successive transmission, the next transmit data is written by setting the MDmn0 bit to 1 when SDRmn data has

Note The SMR01 and SMR03 registers only.

Caution Be sure to clear bits 13 to 9, 7, 4, and 3 (or bits 13 to 6, 4, and 3 for the SMR00, SMR02, SMR10, or

SMR11 register) to "0". Be sure to set bit 5 to "1".

Remark m: Unit number (m = 0, 1), n: Channel number (n = 0 to 3 for m = 0, n = 0, 1 for m = 1),

p: CSI number (p = 00, 20, 21), q: UART number (q = 0, 1), r: IIC number (r = 00, 20)

13.3.4 Serial communication operation setting register mn (SCRmn)

The SCRmn register is a communication operation setting register of channel n. It is used to set a data

transmission/reception mode, phase of data and clock, whether an error signal is to be masked or not, parity bit, start bit,

stop bit, and data length.

Rewriting the SCRmn register is prohibited when the register is in operation (when SEmn = 1).

The SCRmn register can be set by a 16-bit memory manipulation instruction.

Reset signal generation sets the SCRmn register to 0087H.

R01UH0515EJ0120 Rev.1.20

Dec 16, 2016

Figure 13-7. Format of Serial Mode Register mn (SMRmn) (2/2)

Controls inversion of level of receive data of channel n in UART mode

Simplified I

Setting prohibited

Selection of interrupt source of channel n

CHAPTER 13 SERIAL ARRAY UNIT

After reset: 0020H

Setting of operation mode of channel n

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