Renesas RL78 Series User Manual page 221

RL78/G1D
(5) Operation of capture & one-count mode (high-level width measurement)
<1> Operation is enabled (TEmn = 1) by writing 1 to the TSmn bit of timer channel start register m (TSm).
<2> Timer count register mn (TCRmn) holds the initial value until start trigger generation.
<3> Rising edge of the TImn input is detected.
<4> On start trigger detection, the value of 0000H is loaded to the TCRmn register and count starts.
<5> On detection of the falling edge of the TImn input, the value of the TCRmn register is captured to timer data
register mn (TDRmn) and INTTMmn is generated.
Figure 7-28. Operation Timing (In Capture & One-count Mode : High-level Width Measurement)
f
MCK
(f )
TCLK
TSmn (write)
TEmn
TImn input
Rising edge
Falling edge
Start trigger
detection signal
TCRmn
TDRmn
INTTMmn
Remark The timing is shown in Figure 7-28 indicates while the noise filter is not used. By making the noise filter
on-state, the edge detection becomes 2 f
cycle of TImn input. The error per one period occurs be the asynchronous between the period of the
TImn input and that of the count clock (f
R01UH0515EJ0120 Rev.1.20
Dec 16, 2016
<1>
<3>
Edge detection
<2>
Initial value
CHAPTER 7 TIMER ARRAY UNIT
<4>
0000
0000
cycles (it sums up to 3 to 4 cycles) later than the normal
MCK
).
MCK
Edge detection
<5>
– m
m+1
m 1
m
200