Renesas RL78 Series User Manual page 716

RL78/G1D
STOP Mode Setting
Item
System clock
Main system clock f
IH
f
X
f
EX
Subsystem clock f
XT
f
EXS
f
IL
CPU
Code flash memory
Data flash memory
RAM
Port (latch)
Timer array unit
Real-time clock (RTC)
12-bit interval timer
Watchdog timer
Clock output/buzzer output
A/D converter
Serial array unit (SAU)
Serial interface (IICA)
Multiplier and divider/multiply-
accumulator
DMA controller
Power-on-reset function
Voltage detection function
External interrupt
High-speed CRC
CRC
operation
General-purpose
function
CRC
RAM parity error detection
function
RAM guard function
SFR guard function
Illegal-memory access
detection function
Remark Operation stopped: Operation is automatically stopped before switching to the STOP mode.
Operation disabled: Operation is stopped before switching to the STOP mode.
f : High-speed on-chip oscillator clock
IH
f : X1 clock
X
f : XT1 clock
XT
R01UH0515EJ0120 Rev.1.20
Dec 16, 2016
Table 19-2. Operating Statuses in STOP Mode
When STOP Instruction Is Executed While CPU Is Operating on Main System Clock
When CPU Is Operating on
High-speed on-chip oscillator
clock (f )
IH
Clock supply to the CPU is stopped
Stopped
Status before STOP mode was set is retained
Set by bits 0 (WDSTBYON) and 4 (WDTON) of option byte (000C0H), and WUTMMCK0 bit of
subsystem clock supply mode control register (OSMC)
● WUTMMCK0 = 1: Oscillates
● WUTMMCK0 = 0 and WDTON = 0: Stops
● WUTMMCK0 = 0, WDTON = 1, and WDSTBYON = 1: Oscillates
● WUTMMCK0 = 0, WDTON = 1, and WDSTBYON = 0: Stops
Operation stopped
Operation stopped
Operation stopped
Status before STOP mode was set is retained
Operation disabled
Operable
See CHAPTER 11 WATCHDOG TIMER
Operates when the subsystem clock is selected as the clock source for counting and the
RTCLPC bit is 0 (operation is disabled when a clock other than the subsystem clock is selected
and the RTCLPC bit is not 0).
Wakeup operation is enabled (switching to the SNOOZE mode)
Wakeup operation is enabled only for CSI00 and UART0 (switching to the SNOOZE mode)
Operation is disabled for anything other than CSI00 and UART0
Wakeup by address match operable
Operation disabled
Operable
Operation stopped
CHAPTER 19 STANDBY FUNCTION
When CPU Is Operating on
X1 Clock (f )
X
f : Low-speed on-chip oscillator clock
IL
f : External main system clock
EX
f : External subsystem clock
EXS
When CPU Is Operating on
External Main System Clock
(f )
EX
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