Renesas RL78 Series User Manual page 269

RL78/G1D
Master channel
(interval timer mode)
CKm1
Operation clock
CKm0
TSmn
Slave channel
(one-count mode)
CKm1
Operation clock
CKm0
Remark m: Unit number (m = 0), n: Master channel number (n = 0, 2, 4, 6)
p: Slave channel number (n < p
R01UH0515EJ0120 Rev.1.20
Dec 16, 2016
Figure 7-69. Block Diagram of Operation as PWM Function
7)
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CHAPTER 7 TIMER ARRAY UNIT
Timer counter
register mn (TCRmn)
Timer data
register mn (TDRmn)
Timer counter
register mp (TCRmp)
Timer data
register mp (TDRmp)
Interrupt
Interrupt signal
controller
(INTTMmn)
Output
TO0p pin
controller
Interrupt
Interrupt signal
controller
(INTTMmp)
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