Renesas RL78 Series User Manual page 557

RL78/G1D
14.3.5 IICA control register n1 (IICCTLn1)
This register is used to set the operation mode of I
The IICCTLn1 register can be set by a 1-bit or 8-bit memory manipulation instruction. However, the CLDn and DADn
bits are read-only.
Set the IICCTLn1 register, except the WUPn bit, while operation of I
n0 (IICCTLn0) is 0).
Reset signal generation clears this register to 00H.
Address: F0231H (IICCTL01), F0239H (IICCTL11)
Symbol <7>
IICCTLn1 WUPn
WUPn
0
1
To shift to STOP mode when WUPn = 1, execute the STOP instruction at least three f
the WUPn bit (see Figure 14-22 Flow When Setting WUPn = 1).
Clear (0) the WUPn bit after the address has matched or an extension code has been received. The
subsequent communication can be entered by the clearing (0) WUPn bit. (The wait must be released and
transmit data must be written after the WUPn bit has been cleared (0).)
The interrupt timing when the address has matched or when an extension code has been received, while WUPn
= 1, is identical to the interrupt timing when WUPn = 0. (A delay of the difference of sampling by the clock will
occur.) Furthermore, when WUPn = 1, a stop condition interrupt is not generated even if the SPIEn bit is set to
1.
Condition for clearing (WUPn = 0)
● Cleared by instruction (after address match or
extension code reception)
Notes 1. Bits 4 and 5 are read-only.
2. The status of the IICA status register n (IICSn) must be checked and the WUPn bit must be set
SCLAn
SDAAn
Remark
R01UH0515EJ0120 Rev.1.20
Dec 16, 2016
Figure 14-9. Format of IICA Control Register n1 (IICCTLn1) (1/2)
6 <5>
0 CLDn DADn
Stops operation of address match wakeup function in STOP mode.
Enables operation of address match wakeup function in STOP mode.
during the period shown below.
<1>
Check the IICSn operation status and set
WUPn during this period.
n = 0
CHAPTER 14 SERIAL INTERFACE IICA
2
C and detect the statuses of the SCLAn and SDAAn pins.
2
C is disabled (bit 7 (IICEn) of IICA control register
Note 1
After reset: 00H R/W
<4> <3> <2>
SMCn DFCn
Control of address match wakeup
Condition for setting (WUPn = 1)
● Set by instruction (when the MSTSn, EXCn, and
COIn bits are "0", and the STDn bit also "0"
(communication not entered))
A6 A5 A4
The maximum time from reading IICSn to setting
WUPn is the period from <1> to <2>.
1 <0>
0 PRSn
clocks after setting (1)
MCK
Note 2
<2>
A3 A2 A1 A0 R/W
536