Renesas RL78 Series User Manual page 58

RL78/G1D
F F F F F H
F F F 0 0 H
F F E F F H
F F E E 0 H
F F E D F H
F C F 0 0 H
F C E F F H
F 3 0 0 0 H
F 2 F F F H
F 1 0 0 0 H
F 0 F F F H
F 0 8 0 0 H
F 0 7 F F H
Special function register (2nd SFR)
F 0 0 0 0 H
E F F F F H
Data memory
space
2 0 0 0 0 H
1 F F F F H
Program
memory
space
0 0 0 0 0 H
Notes 1. Do not allocate RAM addresses which are used as a stack area, a data buffer, a branch destination of
vector interrupt processing, and a DMA transfer destination/transfer source to the area FFE20H to FFEDFH
when performing self-programming and rewriting the data flash memory.
2. Instructions can be executed from the RAM area excluding the general-purpose register area.
3. When boot swap is not used: Set the option bytes to 000C0H to 000C3H, and the on-chip debug security
When boot swap is used:
4. Writing boot cluster 0 can be prohibited depending on the setting of security (see 25.7 Security Setting).
Caution While RAM parity error resets are enabled (RPERDIS = 0), be sure to initialize RAM areas where data
access is to proceed and the RAM area + 10 bytes when instructions are fetched from RAM areas,
respectively. Reset signal generation sets RAM parity error resets to enabled (RPERDIS = 0). For
details, see 23.3.3 RAM parity error detection function.
R01UH0515EJ0120 Rev.1.20
Dec 16, 2016
Figure 4-1. Memory Map (R5F11AGG)
Special function register (SFR)
256 bytes
General-purpose register
32 bytes
Notes 1, 2
RAM
12 KB
Mirror
39.75 KB
Data flash memory
8 KB
Reserved
2 KB
Reserved
Code flash memory
128 KB
IDs to 000C4H to 000CDH.
Set the option bytes to 000C0H to 000C3H and 010C0H to 010C3H, and the
on-chip debug security IDs to 000C4H to 000CDH and 010C4H to 010CDH.
CHAPTER 4 CPU ARCHITECTURE
1 F F F F H
Program area
0 1 0 C E H
0 1 0 C D H
On-chip debug security
Note 3
ID setting area
10 bytes
0 1 0 C 4 H
0 1 0 C 3 H
Option byte area Note 3
4 bytes
0 1 0 C 0 H
0 1 0 B F H
CALLT table area
64 bytes
0 1 0 8 0 H
0 1 0 7 F H
Vector table area
128 bytes
0 1 0 0 0 H
0 0 F F F H
Program area
0 0 0 C E H
0 0 0 C D H
On-chip debug security
ID setting area Note 3
10 bytes
0 0 0 C 4 H
0 0 0 C 3 H
Note 3
Option byte area
4 bytes
0 0 0 C 0 H
0 0 0 B F H
CALLT table area
64 bytes
0 0 0 8 0 H
0 0 0 7 F H
Vector table area
128 bytes
0 0 0 0 0 H
0 1 F F F H
Boot cluster 1
Note 4
Boot cluster 0
37