Renesas RL78 Series User Manual page 740

RL78/G1D
22.3.2 Voltage detection level register (LVIS)
This register selects the voltage detection level.
This register can be set by a 1-bit or 8-bit memory manipulation instruction.
Reset signal generation input sets this register to 00H/01H/81H
Figure 22-3. Format of Voltage Detection Level Select Register (LVIS)
Address: FFFAAH
Symbol <7>
LVIS LVIMD
Note
LVIMD
2
0
1
Note 2
LVILV
0
1
Notes 1. The reset value changes depending on the reset source and the setting of the option byte.
This register is not cleared (00H) by LVD reset.
The generation of reset signal other than an LVD reset sets as follows.
● When option byte LVIMDS1, LVIMDS0 = 1, 0: 00H
● When option byte LVIMDS1, LVIMDS0 = 1, 1: 81H
● When option byte LVIMDS1, LVIMDS0 = 0, 1: 01H
2. Writing "0" can only be allowed in the interrupt & reset mode (option byte LVIMDS1, LVIMDS0 = 1, 0).
Do not set LVIMD and LVILV in other cases. The value is switched automatically when reset or
interrupt is generated in the interrupt & reset mode.
Cautions 1. Rewrite the value of the LVIS register according to Figures 22-8 and 22-9.
2. Specify the LVD operation mode and detection voltage (V
using the option byte 000C1H.
(000C1H/010C1H). For details about the option byte, see CHAPTER 25 OPTION BYTE.
R01UH0515EJ0120 Rev.1.20
Dec 16, 2016
Note 1
After reset: 00H/01H/81H
6 5
0 0
Interrupt mode
Reset mode
High-voltage detection level (V
Low-voltage detection level (V
CHAPTER 22 VOLTAGE DETECTOR
Note 1
.
R/W
4 3
0 0
Operation mode of voltage detection
LVD detection level
)
LVDH
or V )
LVDL LVD
Figure 22-4 shows the format of the user option byte
2 1 <0>
0 0 LVILV
, V , V ) of each mode by
LVDH LVDL LVD
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