Renesas RL78 Series User Manual page 195

RL78/G1D
Address: F0190H, F0191H (TMR00) to F019EH, F019FH (TMR07)
Symbol 15 14
TMRmn CKS CKS
mn1 mn0
(mn = 02, 04,
06)
Symbol 15 14
TMRmn CKS CKS
mn1 mn0
(mn = 01, 03)
Symbol 15 14
TMRmn CKS CKS
mn1 mn0
(mn = 00, 05,
07)
CKS CKS
mn1 mn0
0 0
0 1
1 0
1 1
Operation clock (f
depending on the setting of the CCSmn bit.
The operation clocks CKm2 and CKm3 can only be selected for channel 1 and 3.
CCS
mn
0 Operation clock (f
1 Valid edge of input signal input from the TImn pin
In channel 5, Valid edge of input signal selected by TIS0
Count clock (f
Note Bit 11 is a read-only bit and fixed to 0. Writing to this bit is ignored.
Cautions 1. Be sure to clear bits 13, 5, and 4 to "0".
2. The timer array unit must be stopped (TTm = 00FFH) if the clock selected for f
(by changing the value of the system clock control register (CKC)), even if the operating clock
specified by using the CKSmn0 and CKSmn1 bits (f
from the TImn pin is selected as the count clock (f
Remark m: Unit number (m = 0), n: Channel number (n = 0 to 7)
R01UH0515EJ0120 Rev.1.20
Dec 16, 2016
Figure 7-11. Format of Timer Mode Register mn (TMRmn) (1/4)
13 12 11 10
0 0 MAST STS
ERmn mn2
13 12 11 10
0 0 SPLIT STS
mn mn2
13 12 11 10
Note
0 CCS 0 STS
1
mn mn2
Selection of operation clock (f
Operation clock CKm0 set by timer clock select register m (TPSm)
Operation clock CKm2 set by timer clock select register m (TPSm)
Operation clock CKm1 set by timer clock select register m (TPSm)
Operation clock CKm3 set by timer clock select register m (TPSm)
) is used by the edge detector. A count clock (f
MCK
Selection of count clock (f
) specified by the CKSmn0 and CKSmn1 bits
MCK
) is used for the counter, output controller, and interrupt controller.
TCLK
After reset: 0000H
9 8 7 6
STS STS CIS CIS
mn1 mn0 mn1 mn0
9 8 7 6
STS STS CIS CIS
mn1 mn0 mn1 mn0
9 8 7 6
STS STS CIS CIS
mn1 mn0 mn1 mn0
MCK
) and a sampling clock are generated
TCLK
) of channel n
TCLK
MCK
TCLK
CHAPTER 7 TIMER ARRAY UNIT
R/W
5 4 3 2
0 0 MD MD
mn3 mn2
5 4 3 2
0 0 MD MD
mn3 mn2
5 4 3 2
0 0 MD MD
mn3 mn2
) of channel n
) or the valid edge of the signal input
).
1 0
MD MD
mn1 mn0
1 0
MD MD
mn1 mn0
1 0
MD MD
mn1 mn0
is changed
CLK
174