Renesas RL78 Series User Manual page 163

RL78/G1D
Table 6-3 shows transition of the CPU clock and examples of setting the SFR registers.
Table 6-3. CPU Clock Transition and SFR Register Setting Examples (1/5)
(1) CPU operating with high-speed on-chip oscillator clock (B) after reset release (A)
Status Transition
(A) → (B)
(2) CPU operating with high-speed system clock (C) after reset release (A)
(The CPU operates with the high-speed on-chip oscillator clock immediately after a reset release (B).)
(Setting sequence of SFR registers)
Setting Flag of SFR Register
Status Transition
(A) → (B) → (C)
(X1 clock: 1 MHz ≤ f ≤ 10 MHz)
X
(A) → (B) → (C)
(X1 clock: 10 MHz < f ≤ 20 MHz)
X
(A) → (B) → (C)
(external main clock)
Notes 1. The clock operation mode control register (CMC) can be written only once by an 8-bit memory
manipulation instruction after reset release.
2. Set the oscillation stabilization time as follows.
● Desired the oscillation stabilization time counter status register (OSTC) oscillation stabilization time
Oscillation stabilization time set by the oscillation stabilization time select register (OSTS)
Caution Set the clock after the supply voltage has reached the operable voltage of the clock to be set (see
CHAPTER 30 ELECTRICAL SPECIFICATIONS).
(3) CPU operating with subsystem clock (D) after reset release (A)
(The CPU operates with the high-speed on-chip oscillator clock immediately after a reset release (B).)
(Setting sequence of SFR registers)
Setting Flag of SFR Register
Status Transition
(A) → (B) → (D)
(XT1 clock)
(A) → (B) → (D)
(external sub clock)
Note The clock operation mode control register (CMC) can be written only once by an 8-bit memory manipulation
instruction after reset release.
Remarks 1. ×: don't care
2. (A) to (J) in Table 6-3 correspond to (A) to (J) in Figure 6-16.
R01UH0515EJ0120 Rev.1.20
Dec 16, 2016
SFR registers do not have to be set (default status after reset release).
Note 1
CMC Register
EXCLK OSCSEL AMPH
0 1 0
0 1 1
1 1 ×
Note
CMC Register
EXCLKS OSCSELS AMPHS1 AMPHS0
0 1 0/1
1 1 ×
CHAPTER 6 CLOCK GENERATOR
SFR Register Setting
OSTS CSC OSTC Register
Register Register
MSTOP
Note 2 0 Must be
checked
Note 2 0 Must be
checked
Note 2 0 Must not be
checked
CSC Waiting for
Register Oscillation
Stabilization
XTSTOP
0/1 0 Necessary
× 0 Necessary
CKC
Register
MCM0
1
1
1
≤
CKC
Register
CSS
1
1
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