Renesas RL78 Series User Manual page 220

RL78/G1D
(4) Operation of one-count mode
<1> Operation is enabled (TEmn = 1) by writing 1 to the TSmn bit.
<2> Timer count register mn (TCRmn) holds the initial value until start trigger generation.
<3> Rising edge of the TImn input is detected.
<4> On start trigger detection, the value of timer data register mn (TDRmn) is loaded to the TCRmn register and
count starts.
<5> When the TCRmn register counts down and its count value is 0000H, INTTMmn is generated and the value of
the TCRmn register becomes FFFFH and counting stops.
f
MCK
(f )
TCLK
TSmn (write)
TEmn
TImn input
Rising edge
Start trigger
detection signal
TCRmn
INTTMmn
Remark The timing is shown in Figure 7-27 indicates while the noise filter is not used. By making the noise filter
on-state, the edge detection becomes 2 f
cycle of TImn input. The error per one period occurs be the asynchronous between the period of the
TImn input and that of the count clock (f
R01UH0515EJ0120 Rev.1.20
Dec 16, 2016
Figure 7-27. Operation Timing (In One-count Mode)
<1>
<3>
Edge detection
<2>
Initial value
Start trigger input wait status
CHAPTER 7 TIMER ARRAY UNIT
<4>
m
cycles (it sums up to 3 to 4 cycles) later than the normal
MCK
).
MCK
<5>
0
FFFF
1
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