RL78/G1D
Address
Special Function Register (SFR) Name
F01B0H
Timer channel enable status register 0
F01B1H
F01B2H
Timer channel start register 0
F01B3H
F01B4H
Timer channel stop register 0
F01B5H
F01B6H
Timer clock select register 0
F01B7H
F01B8H
Timer output register 0
F01B9H
F01BAH
Timer output enable register 0
F01BBH
F01BCH
Timer output level register 0
F01BDH
F01BEH
Timer output mode register 0
F01BFH
F0200H
DMA SFR address register 2
F0201H
DMA SFR address register 3
F0202H
DMA RAM address register 2
F0203H
F0204H
DMA RAM address register 3
F0205H
F0206H
DMA byte count register 2
F0207H
F0208H
DMA byte count register 3
F0209H
F020AH
DMA mode control register 2
F020BH
DMA mode control register 3
F020CH
DMA operation control register 2
F020DH
DMA operation control register 3
F0230H
IICA control register 00
F0231H
IICA control register 01
F0232H
IICA low-level width setting register 0
F0233H
IICA high-level width setting register 0
F0234H
Slave address register 0
F02F0H
Flash memory CRC control register
F02F2H
Flash memory CRC operation result
register
F02FAH
CRC data register
Remark For SFRs in the SFR area, see Table 4-5 SFR List.
R01UH0515EJ0120 Rev.1.20
Dec 16, 2016
Table 4-6. Extended SFR (2nd SFR) List (5/5)
Symbol
TE0L
–
TS0L
–
TT0L
–
TPS0
TO0L
–
TOE0L
–
TOL0L
–
TOM0L
–
DSA2
DSA3
DRA2L
DRA2H
DRA3L
DRA3H
DBC2L
DBC2H
DBC3L
DBC3H
DMC2
DMC3
DRC2
DRC3
IICCTL00
IICCTL01
IICWL0
IICWH0
SVA0
CRC0CTL
PGCRCL
CRCD
CHAPTER 4 CPU ARCHITECTURE
R/W
Manipulable Bit Range
1-bit
TE0
R
–
TS0
R/W
–
TT0
R/W
–
R/W
–
TO0
R/W
–
–
TOE0
R/W
–
TOL0
R/W
–
–
TOM0
R/W
–
–
R/W
–
R/W
–
DRA2
R/W
–
R/W
–
DRA3
R/W
–
R/W
–
DBC2
R/W
–
R/W
–
DBC3
R/W
–
R/W
–
R/W
R/W
R/W
R/W
R/W
R/W
R/W
–
R/W
–
R/W
–
R/W
R/W
–
R/W
–
After Reset
8-bit
16-bit
0000H
–
0000H
–
0000H
–
–
0000H
0000H
–
0000H
–
0000H
–
0000H
–
–
00H
–
00H
00H
00H
00H
00H
00H
00H
00H
00H
–
00H
–
00H
–
00H
–
00H
–
00H
–
00H
–
FFH
–
FFH
–
00H
–
00H
–
0000H
–
0000H
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