Renesas RL78 Series User Manual page 692

RL78/G1D
18.3.1 Interrupt request flag registers (IF0L, IF0H, IF1L, IF1H, IF2L, IF2H, IF3L)
The interrupt request flags are set to 1 when the corresponding interrupt request is generated or an instruction is
executed. They are cleared to 0 when an instruction is executed upon acknowledgment of an interrupt request or upon
reset signal generation.
When an interrupt is acknowledged, the interrupt request flag is automatically cleared and then the interrupt routine is
entered.
The IF0L, IF0H, IF1L, IF1H, IF2L, IF2H, and IF3L registers can be set by a 1-bit or 8-bit memory manipulation
instruction. When the IF0L and IF0H registers, the IF1L and IF1H registers, and the IF2L and IF2H registers are
combined to form 16-bit registers IF0, IF1, and IF2, they can be set by a 16-bit memory manipulation instruction.
Reset signal generation clears these registers to 00H.
Remark If an instruction that writes data to this register is executed, the number of instruction execution clocks
increases by 2 clocks.
Figure 18-2. Format of Interrupt Request Flag Registers (IF0L, IF0H, IF1L, IF1H, IF2L, IF2H, IF3L) (1/2)
Address: FFFE0H After reset: 00H R/W
Symbol <7>
IF0L PIF5
Address: FFFE1H
Symbol <7>
IF0H SREIF0
TMIF01H
Address: FFFE2H
Symbol <7>
IF1L TMIF03
Address: FFFE3H
Symbol <7>
IF1H TMIF04
Address: FFFD0H
Symbol 7
IF2L 0
R01UH0515EJ0120 Rev.1.20
Dec 16, 2016
6 <5>
0 PIF3
After reset: 00H R/W
<6> <5>
SRIF0 STIF0
CSIIF00
IICIF00
After reset: 00H R/W
<6> <5>
TMIF02 TMIF01
After reset: 00H R/W
6 5
0 0
After reset: 00H R/W
6 5
0 0
CHAPTER 18 INTERRUPT FUNCTIONS
4 3
0 0
<4> <3>
DMAIF1 DMAIF0
<4> <3>
SREIF1
TMIF00 IICAIF0
TMIF03H
4 3
0 0
4 <3>
0 PIF6 TMIF07
<2> <1> <0>
PIF0 LVIIF WDTIIF
2 <1> <0>
0 CSIIF21 CSIIF20
IICIF20
<2> <1> <0>
STIF1
SRIF1
<2> <1> <0>
ITIF RTCIF ADIF
<2> <1> <0>
TMIF06 TMIF05
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