Renesas RL78 Series User Manual page 400

RL78/G1D
13.3.3 Serial mode register mn (SMRmn)
The SMRmn register is a register that sets an operation mode of channel n. It is also used to select an operation clock
(f ), specify whether the serial clock (f
MCK
2
simplified I C), and an interrupt source. This register is also used to invert the level of the receive data only in the UART
mode.
Rewriting the SMRmn register is prohibited when the register is in operation (when SEmn = 1). However, the MDmn0
bit can be rewritten during operation.
The SMRmn register can be set by a 16-bit memory manipulation instruction.
Reset signal generation sets the SMRmn register to 0020H.
Address: F0110H, F0111H (SMR00) to F0116H, F0117H (SMR03),
F0150H, F0151H (SMR10), F0152H, F0153H (SMR11)
Symbol 15 14
CKS CCS
SMRmn
mn mn
CKS
mn
0 Operation clock CKm0 set by the SPSm register
1 Operation clock CKm1 set by the SPSm register
Operation clock (f
higher 7 bits of the SDRmn register, a transfer clock (f
CCS
mn
0 Divided operation clock f
1 Clock input f
Transfer clock f
error controller. When CCSmn = 0, the division ratio of operation clock (f
SDRmn register.
STS
mn
Note
0 Only software trigger is valid (selected for CSI, UART transmission, and simplified I
1 Valid edge of the R
Transfer is started when the above source is satisfied after 1 is set to the SSm register.
Note The SMR01 and SMR03 registers only.
Caution Be sure to clear bits 13 to 9, 7, 4, and 3 (or bits 13 to 6, 4, and 3 for the SMR00, SMR02, SMR10, or
SMR11 register) to "0". Be sure to set bit 5 to "1".
Remark m: Unit number (m = 0, 1), n: Channel number (n = 0 to 3 for m = 0, n = 0, 1 for m = 1),
p: CSI number (p = 00, 20, 21), q: UART number (q = 0, 1), r: IIC number (r = 00, 20)
R01UH0515EJ0120 Rev.1.20
Dec 16, 2016
) may be input or not, set a start trigger, an operation mode (CSI, UART, or
SCK
Figure 13-7. Format of Serial Mode Register mn (SMRmn) (1/2)
13 12 11 10
0 0 0 0
Selection of operation clock (f
) is used by the edge detector. In addition, depending on the setting of the CCSmn bit and the
MCK
Selection of transfer clock (f
specified by the CKSmn bit
MCK
from the SCKp pin (slave transfer in CSI mode)
SCK
is used for the shift register, communication controller, output controller, interrupt controller, and
TCLK
Dq pin (selected for UART reception)
X
CHAPTER 13 SERIAL ARRAY UNIT
After reset: 0020H
9 8 7 6
STS SIS
0 0
Note Not
mn mn0
e
) of channel n
MCK
) is generated.
TCLK
) of channel n
TCLK
MCK
Selection of start trigger source
R/W
5 4 3 2
MD MD
1 0 0
mn2 mn1
) is set by the higher 7 bits of the
2
C).
1 0
MD
mn0
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