Renesas RL78 Series User Manual page 591

RL78/G1D
(1) Master device operation
(a) Start ~ Address ~ Data ~ Data ~ Stop (transmission/reception)
(i) When WTIMn = 0
ST AD6 to AD0 R/W ACK
1: IICSn = 1000×110B
2: IICSn = 1000×000B
3: IICSn = 1000×000B (Sets the WTIMn bit to 1)
4: IICSn = 1000××00B (Sets the SPTn bit to 1)
5: IICSn = 00000001B
Note To generate a stop condition, set the WTIMn bit to 1 and change the timing for generating the INTIICAn
interrupt request signal.
Remark : Always generated
: Generated only when SPIEn = 1
×: Don't care
(ii) When WTIMn = 1
ST AD6 to AD0 R/W ACK
1: IICSn = 1000×110B
2: IICSn = 1000×100B
3: IICSn = 1000××00B (Sets the SPTn bit to 1)
4: IICSn = 00000001B
Remark : Always generated
: Generated only when SPIEn = 1
×: Don't care
Remark n = 0
R01UH0515EJ0120 Rev.1.20
Dec 16, 2016
D7 to D0 ACK
1 2
Note
Note
D7 to D0 ACK
1
CHAPTER 14 SERIAL INTERFACE IICA
SPTn = 1
D7 to D0 ACK
3
SPTn = 1
D7 to D0 ACK
2
↓
SP
4 5
↓
SP
3 4
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