Renesas RL78 Series User Manual page 502

RL78/G1D
(2) Operation procedure
Setting the PER0 register
Setting the SPSm register
Setting the SMRmn and SMRmr registers
Setting the SCRmn register
Setting the SDRmn register
Writing to the SSm register
Completing initial setting
Caution Set the RXEmn bit of SCRmn register to 1, and then be sure to set SSmn to 1 after 4 or more
f
MCK
(Selective)
(Essential)
(Selective)
R01UH0515EJ0120 Rev.1.20
Dec 16, 2016
Figure 13-84. Initial Setting Procedure for UART Reception
Starting initial setting
Setting port
clocks have elapsed.
Figure 13-85. Procedure for Stopping UART Reception
Starting setting to stop
TSFmn = 0?
Yes
Writing the STm register
Setting the PER0 register
Stop setting is completed
CHAPTER 13 SERIAL ARRAY UNIT
Release the serial array unit from the
reset status and start clock supply.
Set the operation clock.
Set an operation mode, etc.
Set a communication format.
Set a transfer baud rate (setting the
transfer clock by dividing the operation
clock (f )).
MCK
Enable data input of the target channel
by setting a port register and a port
mode register.
Set the SSmn bit of the target channel to 1 and
set the SEmn bit to 1 (to enable operation).
Become wait for start bit detection.
If there is any data being transferred, wait for
No
their completion.
(If there is an urgent must stop, do not wait)
Write 1 to the STmn bit of the target channel.
(SEmn = 0: to operation stop status)
Reset the serial array unit by stopping the
clock supply to it.
The master transmission is stopped.
Go to the next processing.
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