Renesas RL78 Series User Manual page 539

RL78/G1D
SMRmn
Register
CKSmn PRS PRS
m13 m12
0 X
X
X
X
X
X
X
X
X
X
X
X
1 0
0
0
0
0
0
0
0
1
1
1
1
Note When changing the clock selected for f
after having stopped (serial channel stop register m (STm) = 000FH) the operation of the serial array unit
(SAU).
Remarks 1. X: Don't care
2. m: Unit number (m = 0, 1), n: Channel number (n = 0), mn = 00, 10
Here is an example of setting an I
2
I C Transfer Mode
(Desired Transfer Rate)
100 kHz
400 kHz
1 MHz
Note The error cannot be set to about 0% because the duty ratio of the SCL signal is 50%.
R01UH0515EJ0120 Rev.1.20
Dec 16, 2016
Table 13-5. Selection of Operation Clock For Simplified I
SPSm Register
PRS PRS PRS PRS
m11 m10 m03 m02
X X X 0 0
X X X 0 0
X X X 0 0
X X X 0 0
X X X 0 1
X X X 0 1
X X X 0 1
X X X 0 1
X X X 1 0
X X X 1 0
X X X 1 0
X X X 1 0
0 0 0 X X
0 0 1 X X
0 1 0 X X
0 1 1 X X
1 0 0 X X
1 0 1 X X
1 1 0 X X
1 1 1 X X
0 0 0 X X
0 0 1 X X
0 1 0 X X
0 1 1 X X
Other than above
2
C transfer rate where f
Operation Clock (f )
MCK
f /2
CLK
f
CLK
f
CLK
PRS PRS
m01 m00
0 0 f
CLK
0 1 f /2
CLK
2
1 0 f /2
CLK
3
1 1 f /2
CLK
4
0 0 f /2
CLK
5
0 1 f /2
CLK
6
1 0 f /2
CLK
7
1 1 f /2
CLK
8
0 0 f /2
CLK
9
0 1 f /2
CLK
10
1 0 f /2
CLK
11
1 1 f /2
CLK
X X f
CLK
X X f /2
CLK
2
X X f /2
CLK
3
X X f /2
CLK
4
X X f /2
CLK
5
X X f /2
CLK
6
X X f /2
CLK
7
X X f /2
CLK
8
X X f /2
CLK
9
X X f /2
CLK
10
X X f /2
CLK
11
X X f /2
CLK
Setting prohibited
(by changing the system clock control register (CKC) value), do so
CLK
= f = 32 MHz.
MCK CLK
f = 32 MHz
CLK
SDRmn[15:9] Calculated
Transfer Rate
79 100 kHz
41 380 kHz
18 0.84 MHz
CHAPTER 13 SERIAL ARRAY UNIT
2
C
Note
Operation Clock (f )
MCK
f = 32 MHz
CLK
32 MHz
16 MHz
8 MHz
4 MHz
2 MHz
1 MHz
500 kHz
250 kHz
125 kHz
62.5 kHz
31.25 kHz
15.63 kHz
32 MHz
16 MHz
8 MHz
4 MHz
2 MHz
1 MHz
500 kHz
250 kHz
125 kHz
62.5 kHz
31.25 kHz
15.63 kHz
Error from Desired Transfer
Rate
0.0%
Note
5.0%
Note
16.0%
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