Renesas RL78 Series User Manual page 567

RL78/G1D
14.5.5 Stop condition
When the SCLAn pin is at high level, changing the SDAAn pin from low level to high level generates a stop condition.
A stop condition is a signal that the master device generates to the slave device when serial transfer has been
completed. When the device is used as a slave, stop conditions can be detected.
A stop condition is generated when bit 0 (SPTn) of IICA control register n0 (IICCTLn0) is set to 1. When the stop
condition is detected, bit 0 (SPDn) of the IICA status register n (IICSn) is set to 1 and INTIICAn is generated when bit 4
(SPIEn) of the IICCTLn0 register is set to 1.
Remark n = 0
R01UH0515EJ0120 Rev.1.20
Dec 16, 2016
Figure 14-19. Stop Condition
H
SCLAn
SDAAn
CHAPTER 14 SERIAL INTERFACE IICA
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