RL78/F13, F14
5.6.2 Example of Setting X1 Oscillator
After a reset release, the CPU/peripheral hardware clock (f
oscillator clock. To subsequently change the clock to the X1 oscillation clock, set the oscillator and start oscillation by using
the clock operation mode control register (CMC) and clock operation status control register (CSC) and wait for oscillation to
stabilize by using the oscillation stabilization time counter status register (OSTC). After the oscillation stabilizes, set the X1
oscillation clock to f
by using the system clock control register (CKC).
CLK
[Register settings] Set the registers in the following order.
<1> Set the OSCSEL bit of the CMC register to 1, except for the cases where the frequency is equal or more than 10MHz,
in such cases set the AMPH bit to 1, to operate the X1 oscillator.
7
EXCLK
CMC
0
<2> Using the OSTS register, select the oscillation stabilization time of the X1 oscillator at releasing of the STOP mode.
Example: Setting values when a wait of at least 102.4
7
OSTS
0
<3> Clear (0) the MSTOP bit of the CSC register to start oscillating the X1 oscillator.
7
MSTOP
CSC
0
<4> Use the OSTC register to wait for oscillation of the X1 oscillator to stabilize.
Example: Wait until the bits reach the following values when a wait of at least 102.4
resonator.
7
MOST8
OSTC
1
<5> Use the MCM0 bit of the CKC register to specify the X1 oscillation clock as the CPU/peripheral hardware clock.
7
CLS
CKC
0
<6> Use the MCS bit of the CKC register to confirm that f
hardware clock (MCS = 1).
7
CLS
CKC
0
R01UH0368EJ0210 Rev.2.10
Dec 10, 2015
6
5
OSCSEL
EXCLKS
OSCSELS
1
0
6
5
0
0
6
5
XTSTOP
1
0
6
5
MOST9
MOST10
MOST11
1
1
6
5
CSS
MCS
MCM0
0
0
6
5
CSS
MCS
MCM0
0
1
CHAPTER 5 CLOCK GENERATOR
) always starts operating with the high-speed on-chip
CLK
4
3
2
AMPHS1
0
0
0
s is set based on a 10 MHz resonator.
4
3
2
OSTS2
0
0
0
4
3
2
0
0
0
4
3
2
MOST13
MOST15
0
0
0
4
3
2
1
0
0
(X1 oscillation clock) is selected as the CPU/peripheral
MX
4
3
2
1
0
0
1
0
AMPHS0
AMPH
0
1
1
0
OSTS1
OSTS0
1
0
1
0
HIOSTOP
0
0
s is set based on a 10 MHz
1
0
MOST17
MOST18
0
0
1
0
0
0
1
0
0
0
404