Renesas RL78 Series User Manual page 531

RL78/G1D
13.7.3 Data reception
Data reception is an operation to receive data to the target for transfer (slave) after transmission of an address field.
After all data are received to the slave, a stop condition is generated and the bus is released.
2
Simplified I C
Target channel Channel 0 of SAU0
Pins used SCL00, SDA00
Interrupt INTIIC00
Transfer end interrupt only (Setting the buffer empty interrupt is prohibited.)
Error detection flag Overrun error detection flag (OVFmn) only
Transfer data length 8 bits
Note 2
Transfer rate Max. f
However, the following condition must be satisfied in each mode of I
● Max. 1 MHz (fast mode plus)
● Max. 400 kHz (fast mode)
● Max. 100 kHz (standard mode)
Data level Non-reversed output (default: high level)
Parity bit No parity bit
Stop bit Appending 1 bit (ACK transmission)
Data direction MSB first
Notes 1. To perform communication via simplified I
POM14 = 1) with the port output mode register (POM0, POM1). For details, see 5.3 Registers Controlling
Port Function and 5.5 Register Settings When Using Alternate Function.
When IIC00, IIC20 are communicating with an external device with a different potential, set the N-ch open-
drain output (V
For details, see 5.4.5 Handling different potential (1.8 V, 2.5 V) by using I/O buffers.
2. Use this operation within a range that satisfies the conditions above and the peripheral functions
characteristics in the electrical specifications (see CHAPTER 30 ELECTRICAL SPECIFICATIONS).
Remark m: Unit number (m = 0, 1), n: Channel number (n = 0), mn = 00, 10
R01UH0515EJ0120 Rev.1.20
Dec 16, 2016
IIC00
Note 1
/4 [Hz] (SDRmn[15:9] = 1 or more)
MCK
tolerance) mode (POMxx = 1) also for the clock input/output pins (SCL00, SCL20).
DD
CHAPTER 13 SERIAL ARRAY UNIT
Channel 0 of SAU1
SCL20, SDA20
INTIIC20
f : Operation clock frequency of target channel
MCK
2
C, set the N-ch open-drain output (V
IIC20
Note 1
2
C.
tolerance) mode (POM11,
DD
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