Renesas RL78 Series User Manual page 98

RL78/G1D
ES: word [B], ES: word [C]
<1> <2> <3>
Instruction code
OP-code
Low Addr.
<2>
High Addr.
The ES register <1> specifies a 64-Kbyte area within the overall
1-Mbyte space as the four higher-order bits, X, of the address range.
"word" <2> specifies the address where the target array of word-sizeddata
starts in the 64-Kbyte area specified in the ES register <1>.
Either register <3> specifies an offset within the array tothe target location
in memory.
ES: word [BC]
<1> <2>
Instruction code
OP-code
Low Addr.
<2>
High Addr.
The ES register <1> specifies a 64-Kbyte area within the
overall 1-Mbyte space as the four higher-order bits, X, of
the address range.
"word" <2> specifies the address where the target array of
word-sized data starts in the 64-Kbyte area specified in the
ES register <1>.
A pair of registers <3> specifies an offset within the array
to the target location in memory.
R01UH0515EJ0120 Rev.1.20
Dec 16, 2016
Figure 4-32. Example of ES:word[B], ES:word[C]
<1> <2> <3>
<3>
r(B/C)
<2>
Address of a word within an array
<1>
ES
Figure 4-33. Example of ES:word[BC]
<3>
<3>
rp(BC)
<2>
Address of a word within an array
X0000H
<1> <1>
ES
CHAPTER 4 CPU ARCHITECTURE
<3>
Offset
X0000H
Specifies a
<1>
64-Kbyte area
Target memory
<3>
Offset
Specifies a
64-Kbyte area
XFFFFH
Target memory
X0000H
Memory
XFFFFH
Array of
word-sized
X0000H
Memory
Array of
word-sized
data
data
77