Renesas RL78 Series User Manual page 246

RL78/G1D
Figure 7-50. Example of Set Contents of Registers During Operation as Frequency Divider
(a) Timer mode register 00 (TMR00)
15 14
TMR00
CKS0n1 CKS0n0
1/0 0
Operation clock (f
00B: Selects CK00 as operation clock of channel 0.
10B: Selects CK01 as operation clock of channel 0.
(b) Timer output register 0 (TO0)
Bit 0
TO0
TO00
1/0
(c) Timer output enable register 0 (TOE0)
Bit 0
TOE0
TOE00
1/0
(d) Timer output level register 0 (TOL0)
Bit 0
TOL0
TOL00
0
(e) Timer output mode register 0 (TOM0)
Bit 0
TOM0
TOM00
0
R01UH0515EJ0120 Rev.1.20
Dec 16, 2016
13 12 11 10
CCS00 STS002 STS001
0 1 0 0
Count clock selection
1: Selects the TI00 pin input valid edge.
) selection
MCK
0: Outputs 0 from TO00.
1: Outputs 1 from TO00.
0: Stops the TO00 output operation by counting operation.
1: Enables the TO00 output operation by counting operation.
0: Cleared to 0 when master channel output mode (TOM00 = 0)
0: Sets master channel output mode.
9 8 7 6 5
STS000 CIS001 CIS000
0 0 1/0 1/0 0
Operation mode of channel 0
000B: Interval timer
Selection of TI00 pin input edge
00B: Detects falling edge.
01B: Detects rising edge.
10B: Detects both edges.
11B: Setting prohibited
Start trigger selection
000B: Selects only software start.
CHAPTER 7 TIMER ARRAY UNIT
4 3 2 1
MD003 MD002 MD001
0 0 0 0
Setting of operation when counting is started
0: Neither generates INTTM00 nor inverts
timer output when counting is started.
1: Generates INTTM00 and inverts timer
output when counting is started.
0
MD000
1/0
225