Renesas RL78 Series User Manual page 376

RL78/G1D
12.7.4 Setup when temperature sensor output/internal reference voltage output is selected (example for software
trigger mode and one-shot conversion mode)
Figure 12-32. Setup when temperature sensor output/internal reference voltage output is selected
Start of setup
PER0 register setting
● ADM0 register setting
● ADM1 register setting
● ADM2 register setting
● ADUL/ADLL register setting
● ADS register setting
(The order of the settings is
irrelevant.)
Reference voltage stabilization
wait time count A
ADCE bit setting
Stabilization wait time count B
ADCS bit setting
Start of A/D conversion
End of A/D conversion
ADCS bit setting
Start of A/D conversion
End of A/D conversion
Storage of conversion results in
the ADCR and ADCRH registers
Note Depending on the settings of the ADRCK bit and ADUL/ADLL registers, there is a possibility of no interrupt
signal being generated. In this case, the results are not stored in the ADCR and ADCRH registers.
Caution This setting can be used only in HS (high-speed main) mode.
R01UH0515EJ0120 Rev.1.20
Dec 16, 2016
The ADCEN bit of the PER0 register is set (1), and supplying the clock
starts.
● ADM0 register
FR2 to FR0, LV1, and LV0 bits: These are used to specify the A/D
ADSCM bit: Select mode/scan mode
● ADM1 register
ADTMD1 and ADTMD0 bits:
ADSCM bit: Sequential conversion mode/one-shot conversion mode
● ADM2 register
ADREFP1, ADREFP0, and ADREFM bits: These are used to select the
ADRCK bit: This is used to select the range for the A/D conversion result
comparison value generated by the interrupt signal from
AREA1, AREA3, and AREA2.
ADTYP bit: 8-bit/10-bit resolution
● ADUL/ADLL register
These are used to specify the upper limit and lower limit A/D conversion
result comparison values.
● ADS register
ADISS and ADS4 to ADS0 bits: These are used to select temperature
The reference voltage stabilization wait time A may be required
if the values of the ADREFP1 and ADREFP0 bits are changed.
A wait is not required if the values of ADREFP1 and ADREFP0 are changed to 0 and 0 or 0 and 1,
respectively.
Setting the values of ADREFP1 and ADREFP0 to 1 and 0, respectively is prohibited.
The ADCE bit of the ADM0 register is set (1), and the system enters the
A/D conversion standby status.
The reference voltage stabilization wait time (1
After counting up to the stabilization wait time B ends, the ADCS bit of the
ADM0 register is set (1), and A/D conversion starts
The A/D conversion end interrupt (INTAD) will be generated.
After ADISS is set (1), the initial conversion result cannot be used.
The ADCS bit of the ADM0 register is set (1), and A/D conversion starts.
The A/D conversion end interrupt (INTAD) is generated.
The conversion results are stored in the ADCR and ADCRH registers.
CHAPTER 12 A/D CONVERTER
conversion time.
These are used to specify the software
trigger mode.
reference voltage.
sensor 0 output or internal reference
voltage output.
s) is counted by the software.
Note
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