Renesas RL78 Series User Manual page 725

RL78/G1D
20.1 Timing of Reset Operation
This LSI is reset by input of the low level on the RESET pin and released from the reset state by input of the high level
on the RESET pin. After reset processing, execution of the program with the high-speed on-chip oscillator clock as the
operating clock starts.
High-speed on-chip
oscillator clock
High-speed system clock
(when X1 oscillation is selected)
CPU status
RESET
Internal reset signal
Port pin
(except P130)
Port pin
(P130)
Release from the reset state is automatic in the case of a reset due to a watchdog timer overflow, execution of an
illegal instruction, detection of a RAM parity error, or detection of illegal memory access. After reset processing, execution
of the program with the high-speed on-chip oscillator clock as the operating clock starts.
Figure 20-3. Timing of Reset Due to Watchdog Timer Overflow, Execution of Illegal Instruction, Detection of RAM
High-speed on-chip
oscillator clock
High-speed system clock
(when X1 oscillation is selected)
CPU status
Watchdog timer overflow/
Execution of illegal instruction/
Detection of RAM parity error/
Detection of illegal memory access
Internal reset signal
Port pin
(except P130)
Port pin
(P130)
(Notes and Caution are listed on the next page.)
R01UH0515EJ0120 Rev.1.20
Dec 16, 2016
Figure 20-2. Timing of Reset by RESET Input
Normal operation
Delay
Parity Error, or Detection of Illegal Memory Access Overflow
Normal operation
CHAPTER 20 RESET FUNCTION
Wait for oscillation
accuracy stabilization
Reset period
(oscillation
stop)
Reset processing for release from the external reset state
Hi-Z
Note1
Wait for oscillation
accuracy stabilization
Reset period
Reset processing
(oscillation stop)
0.0511 ms (typ.)
0.0701 ms (max.)
Hi-Z
Note1
Starting X1 oscillation is specified by software.
Normal operation
(high-speed on-chip oscillator clock)
Note3
Starting X1 oscillation is specified by software
Normal operation
(high-speed on-chip oscillator clock)
Note3
Note2
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