Renesas RL78 Series User Manual page 774

RL78/G1D
24.1 Regulator Overview
The RL78/G1D contains a circuit for operating the device with a constant voltage. At this time, in order to stabilize the
regulator output voltage, connect the REGC pin to V
characteristics, since it is used to stabilize internal voltage.
Caution Keep the wiring length as short as possible for the broken-line part in the above figure.
The regulator output voltage, see Table 24-1.
Mode
LV (low voltage main) mode
LS (low-speed main) mode
HS (high-speed main) mode
Note When it shifts to the subsystem clock operation or STOP mode during the on-chip debugging, the regulator output
voltage is kept at 2.1 V (not decline to 1.8 V).
R01UH0515EJ0120 Rev.1.20
Dec 16, 2016
CHAPTER 24 REGULATOR
SS
Table 24-1. Regulator Output Voltage Conditions
Output Voltage
1.8 V
1.8 V In STOP mode
When both the high-speed system clock (f
oscillator clock (f
(f )
SUB
When both the high-speed system clock (f
oscillator clock (f
with the subsystem clock (f
2.1 V Other than above (include during OCD mode)
via a capacitor (0.47 to 1 µF). Also, use a capacitor with good
REGC
V
SS
Condition
–
) are stopped during CPU operation with the subsystem clock
IH
) are stopped during the HALT mode when the CPU operation
IH
) has been set
SUB
CHAPTER 24 REGULATOR
) and the high-speed on-chip
MX
) and the high-speed on-chip
MX
Note
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