Renesas RL78 Series User Manual page 450

16-bit single-chip microcontrollers
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RL78/G1D
Figure 13-47. Flowchart of Master Transmission/Reception (in Continuous Transmission/Reception Mode)
Write 1 to MDmn0 bit
Remark
<1> to <8> in the figure correspond to <1> to <8> in Figure 13-46 Timing Chart of Master
Transmission/Reception (in Continuous Transmission/Reception Mode).
R01UH0515EJ0120 Rev.1.20
Dec 16, 2016
Starting setting
<1>
SAU default setting
Setting
transmission/reception data
Enables interrupt
Writing dummy data to
<2>
SIOp (=SDRmn[7:0])
Wait for transmission/reception
completes
<3>
<6>
Buffer empty/transfer end interrupt
BFFmn = 1?
Yes
Reading reception data from
<4>
SIOp (=SDRmn[7:0])
<7>
Subtract -1 from number of
transmit data
= 0
Number of
communication data?
≥ 2
Writing transmit data to
SIOp (=SDRmn[7:0])
RETI
No
Number of communication
data = 0?
Yes
Yes
Continuing Communication?
No
Disable interrupt (MASK)
<8>
Write 1 to STmn bit
End of communication
CHAPTER 13 SERIAL ARRAY UNIT
For the initial setting, refer to Figure 13-40.
(Select buffer empty interrupt)
Setting storage data and number of data for transmission/reception data
(Storage area, Transmission data pointer, Reception data, Number of
communication data and Communication end flag are optionally set on the
internal RAM by the software)
Clear interrupt request flag (XXIF), reset interrupt mask (XXMK) and set interrupt
enable (EI)
Read transmit data from storage area and write it
to SIOp. Update transmit data pointer.
When transmission/reception interrupt is generated, it
moves to interrupt processing routine
No
Except for initial interrupt, read data received then write them
to storage area, and update receive data pointer
If transmit data is left (number of communication data is
equal or grater than 2), read them from storage area then
= 1
write into SIOp, and update transmit data pointer.
If it's waiting for the last data to receive (number of
communication data is equal to 1), change interrupt timing
to communication end
<5>
Clear MDmn0 bit to 0
Writing to SIOp makes SOp
and SCKp signals out
(communication starts)
429

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