Renesas RL78 Series User Manual page 395

RL78/G1D
13.2.1 Shift register
This is a 9-bit register that converts parallel data into serial data or vice versa.
In case of the UART communication of nine bits of data, nine bits (bits 0 to 8) are used
During reception, it converts data input to the serial pin into parallel data.
When data is transmitted, the value set to this register is output as serial data from the serial output pin.
The shift register cannot be directly manipulated by program.
To read or write the shift register, use the lower 8/9 bits of serial data register mn (SDRmn).
13.2.2 Lower 8/9 bits of the serial data register mn (SDRmn)
The SDRmn register is the transmit/receive data register (16 bits) of channel n. Bits 8 to 0 (lower 9 bits)
to 0 (lower 8 bits) function as a transmit/receive buffer register, and bits 15 to 9 are used as a register that sets the division
ratio of the operation clock (f
When data is received, parallel data converted by the shift register is stored in the lower 8/9 bits. When data is to be
transmitted, set transmit to be transferred to the shift register to the lower 8/9 bits.
The data stored in the lower 8/9 bits of this register is as follows, depending on the setting of bits 0 and 1 (DLSmn0,
DLSmn1) of serial communication operation setting register mn (SCRmn), regardless of the output sequence of the data.
● 7-bit data length (stored in bits 0 to 6 of SDRmn register)
● 8-bit data length (stored in bits 0 to 7 of SDRmn register)
● 9-bit data length (stored in bits 0 to 8 of SDRmn register)
The SDRmn register can be read or written in 16-bit units.
The lower 8/9 bits of the SDRmn register can be read or written
communication mode.
● CSIp communication ... SIOp (CSIp data register)
● UARTq reception ... RXDq (UARTq receive data register)
● UARTq transmission ... TXDq (UARTq transmit data register)
● IICr communication ... SIOr (IICr data register)
Reset signal generation clears the SDRmn register to 0000H.
Notes 1. Only UART0 can be specified for the 9-bit data length.
2. When operation is stopped (SEmn = 0), do not rewrite SDRmn[7:0] by an 8-bit memory manipulation
instruction (SDRmn[15:9] are all cleared to 0).
Remarks 1. After data is received, "0" is stored in bits 0 to 8 in bit portions that exceed the data length.
2. m: Unit number (m = 0, 1), n: Channel number (n = 0 to 3 for m = 0, n = 1 for m = 1),
p: CSI number (p = 00, 20, 21), q: UART number (q = 0, 1), r: IIC number (r = 00, 20)
R01UH0515EJ0120 Rev.1.20
Dec 16, 2016
Shift register
).
MCK
CHAPTER 13 SERIAL ARRAY UNIT
8 7 6 5 4
Note 1
Note 2
as the following SFR, depending on the
Note 1
.
3 2 1 0
Note 1
or bits 7
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