Renesas RL78 Series User Manual page 699

RL78/G1D
18.3.4 External interrupt rising edge enable registers (EGP0), external interrupt falling edge enable registers (EGN0)
These registers specify the valid edge for INTP0, INTP3, INTP5 and NTP6.
The EGP0 and EGN0 registers can be set by a 1-bit or 8-bit memory manipulation instruction.
Reset signal generation clears these registers to 00H.
Figure 18-5. Format of External Interrupt Rising Edge Enable Register (EGP0) and External Interrupt Falling Edge
Enable Register (EGN0)
Address: FFF38H After reset: 00H
Symbol 7
EGP0 0
Address: FFF39H After reset: 00H
Symbol 7
EGN0 0
EGP0
0
0
1
1
Table 18-3 shows the ports corresponding to the EGPn and EGNn bits.
Table 18-3. Interrupt Request Signals Corresponding to EGPn and EGNn bits
EGP0
EGP3
EGP5
EGP6
Caution When the input port pins used for the external interrupt functions are switched to the output
mode, the INTPn interrupt might be generated upon detection of a valid edge. When switching
the input port pins to the output mode, set the port mode register (PMxx) to 0 after disabling
the edge detection (by setting EGPn and EGNn to 0).
Remarks 1. For edge detection port, see 3.1 Port Function.
2. n = 0, 3, 5, 6
R01UH0515EJ0120 Rev.1.20
Dec 16, 2016
R/W
6 5
EGP6 EGP5
R/W
6 5
EGN6 EGN5
EGN0 INTPn pin valid edge selection (n = 0, 3, 5, and 6)
0 Edge detection disabled
1 Falling edge
0 Rising edge
1 Both rising and falling edges
Detection Enable Bit
CHAPTER 18 INTERRUPT FUNCTIONS
4 3 2
0 EGP3 0
4 3 2
0 EGN3 0
EGN0 INTP0
EGN3 INTP3
EGN5 INTP5
EGN6 INTP6
1 0
0 EGP0
1 0
0 EGN0
Interrupt Request Signal
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