Renesas RL78 Series User Manual page 611

RL78/G1D
14.6 Timing Charts
2
When using the I C bus mode, the master device outputs an address via the serial bus to select one of several slave
devices as its communication partner.
After outputting the slave address, the master device transmits the TRCn bit (bit 3 of the IICA status register n (IICSn)),
which specifies the data transfer direction, and then starts serial communication with the slave device.
Figures 14-32 and 14-33 show timing charts of the data communication.
The IICA shift register n (IICAn)'s shift operation is synchronized with the falling edge of the serial clock (SCLAn). The
transmit data is transferred to the SO latch and is output (MSB first) via the SDAAn pin.
Data input via the SDAAn pin is captured into IICAn at the rising edge of SCLAn.
Remark n = 0
R01UH0515EJ0120 Rev.1.20
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