Renesas RL78 Series User Manual page 374

RL78/G1D
12.7.2 Setting up hardware trigger no-wait mode
Start of setup
PER0 register setting
ADPC and PMC register settings
PM register setting
● ADM0 register setting
● ADM1 register setting
● ADM2 register setting
● ADUL/ADLL register settings
● ADS register setting
(The order of the settings is
irrelevant.)
Reference voltage stabilization
wait time count A
ADCE bit setting
Reference voltage stabilization
wait time count B
ADCS bit setting
Hardware trigger standby status
Start of A/D conversion by
generating a hardware trigger
The A/D conversion operations are performed.
End of A/D conversion
Storage of conversion results in
the ADCR and ADCRH registers
Note Depending on the settings of the ADRCK bit and ADUL/ADLL registers, there is a possibility of no interrupt
signal being generated. In this case, the results are not stored in the ADCR and ADCRH registers.
R01UH0515EJ0120 Rev.1.20
Dec 16, 2016
Figure 12-30. Setting up Hardware Trigger No-Wait Mode
The ADCEN bit of the PER0 register is set (1), and supplying the clock starts.
The ports are set to analog input.
ANI0 to ANI3 pins: Set using the ADPC register.
ANI16 to ANI19 pins: Set using the PMC register.
The ports are set to the input mode.
● ADM0 register
FR2 to FR0, LV1, and LV0 bits: These are used to specify the A/D conversion time.
ADMD bit: Select mode/scan mode
● ADM1 register
ADTMD1 and ADTMD0 bits: These are used to specify the hardware trigger no-wait
ADSCM bit: Sequential conversion mode/one-shot conversion mode
● ADM2 register
ADREFP1, ADREFP0, and ADREFM bits: These are used to select the reference
ADRCK bit: This is used to select the range for the A/D conversion result comparison
value generated by the interrupt signal from AREA1, AREA3, and AREA2.
ADTYP bit: 8-bit/10-bit resolution
● ADUL/ADLL registers
These are used to specify the upper limit and lower limit of A/D conversion result
comparison values.
● ADS register
ADS4 to ADS0 bits: These are used to select the analog input channels.
The reference voltage stabilization wait time indicated by A below may be required
if the values of the ADREFP1 and ADREFP0 bits are changed.
If the values of ADREFP1 and ADREFP0 are changed to 1 and 0, respectively: A = 5
A wait is not required if the values of ADREFP1 and ADREFP0 are changed to 0 and 0 or 0 and 1,
respectively.
The ADCE bit of the ADM0 register is set (1), and the system enters the A/D conversion
standby status.
The reference voltage stabilization wait time (1
After counting up the reference voltage
register is set (1), and the system enters the hardware trigger standby status.
The A/D conversion end interrupt (INTAD) is generated.
The conversion results are stored in the ADCR and ADCRH registers.
CHAPTER 12 A/D CONVERTER
mode.
voltage.
s) is counted by the software.
stabilization wait time B ends, the ADCS bit of the ADM0
Note
s
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