Renesas RL78 Series User Manual page 546

RL78/G1D
(11) Start condition generator
This circuit generates a start condition when the STTn bit is set to 1.
However, in the communication reservation disabled status (IICRSVn bit = 1), when the bus is not released (IICBSYn
bit = 1), start condition requests are ignored and the STCFn bit is set to 1.
(12) Stop condition generator
This circuit generates a stop condition when the SPTn bit is set to 1.
(13) Bus status detector
This circuit detects whether or not the bus is released by detecting start conditions and stop conditions.
However, as the bus status cannot be detected immediately following operation, the initial status is set by the
STCENn bit.
Remarks 1. STTn bit:
SPTn bit:
IICRSVn bit:
IICBSYn bit:
STCFn bit:
STCENn bit:
2. n = 0
R01UH0515EJ0120 Rev.1.20
Dec 16, 2016
Bit 1 of IICA control register n0 (IICCTLn0)
Bit 0 of IICA control register n0 (IICCTLn0)
Bit 0 of IICA flag register n (IICFn)
Bit 6 of IICA flag register n (IICFn)
Bit 7 of IICA flag register n (IICFn)
Bit 1 of IICA flag register n (IICFn)
CHAPTER 14 SERIAL INTERFACE IICA
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