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Renesas RL78 Series User Manual

Renesas RL78 Series User Manual

16-bit single-chip microcontrollers

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RL78/G1D

16

16-Bit Single-Chip Microcontrollers

All information contained in these materials, including products and product specifications,

represents information on the product at the time of publication and is subject to change by

Renesas Electronics Corp. without notice. Please review the latest information published by

Renesas Electronics Corp. through various means, including the Renesas Electronics Corp.

website (http://www.renesas.com).

www.renesas.com

User's Manual: Hardware

Rev.1.20 Dec 2016

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Summary of Contents for Renesas RL78 Series

Page 1 All information contained in these materials, including products and product specifications, represents information on the product at the time of publication and is subject to change by Renesas Electronics Corp. without notice. Please review the latest information published by Renesas Electronics Corp. through various means, including the Renesas Electronics Corp.
Page 2 Renesas Electronics products are not subject to radiation resistance design. Please be sure to implement safety measures to guard them against the possibility of physical injury, and injury or damage caused by fire in the event of the failure of a Renesas Electronics product, such as safety design for hardware and software including but not limited to redundancy, fire control and malfunction prevention, appropriate treatment for aging degradation or any other appropriate measures.
Page 3 NOTES FOR CMOS DEVICES (1) VOLTAGE APPLICATION WAVEFORM AT INPUT PIN: Waveform distortion due to input noise or a reflected wave may cause malfunction. If the input of the CMOS device stays in the area between VIL (MAX) and VIH (MIN) due to noise, etc., the device may malfunction. Take care to prevent chattering noise from entering the device when the input level is fixed, and also in the transition period when the input level passes through the area between VIL (MAX) and VIH (MIN).
Page 4 How to Use This Manual Readers This manual is intended for user engineers who wish to understand the functions of the RL78/G1D and design and develop application systems and programs for these devices. ● 48-pin: R5F11AGG R5F11AGH R5F11AGJ Purpose This manual is intended to give users an understanding of the functions described in the Organization below.
Page 5 Conventions Data significance: Higher digits on the left and lower digits on the right Active low representations: ×××(overscore over pin and signal name) Note: Footnote for item marked with Note in the text Caution: Information requiring particular attention Remark: Supplementary information ...
Page 6 All trademarks and registered trademarks are the property of their respective owners. Bluetooth is a trademark of Bluetooth SIG, Inc. U.S.A. EEPROM is a trademark of Renesas Electronics Corporation. SuperFlash is a registered trademark of Silicon Storage Technology, Inc. in several countries including the United States and Japan.
Page 7: Table Of Contents
CONTENTS CHAPTER 1 OUTLINE ..........................1 1.1 Features ............................1 1.2 List of Part Numbers ........................4 1.3 Pin Configuration (Top View) ......................5 1.4 Pin Identification ..........................6 1.5 Block Diagram ..........................7 1.6 Outline of Functions ........................8 CHAPTER 2 CONNECTION BETWEEN MCU AND RF TRANSCEIVER .........
Page 8 4.3.1 Relative addressing .......................... 67 4.3.2 Immediate addressing ........................67 4.3.3 Table indirect addressing ......................... 68 4.3.4 Register direct addressing ........................ 68 4.4 Addressing for Processing Data Addresses ................69 4.4.1 Implied addressing ........................... 69 4.4.2 Register addressing ......................... 69 4.4.3 Direct addressing ..........................
Page 9 5.4.2 Reading from I/O port ........................101 5.4.3 Operations on I/O port ........................101 5.4.4 Handling different potential (1.8 V, 2.5 V) by using EVDD ≤ VDD ..........102 5.4.5 Handling different potential (1.8 V, 2.5 V) by using I/O buffers ............102 5.5 Register Settings When Using Alternate Function ..............
Page 10 CHAPTER 7 TIMER ARRAY UNIT ...................... 156 7.1 Functions of Timer Array Unit ....................157 7.1.1 Independent channel operation function ..................157 7.1.2 Simultaneous channel operation function ..................158 7.1.3 8-bit timer operation function (channel 1 and 3 only) ..............159 7.2 Configuration of Timer Array Unit ....................
Page 11 7.8.1 Operation as interval timer/square wave output ................212 7.8.2 Operation as external event counter ....................218 7.8.3 Operation as frequency divider (channel 0 of unit 0 only) .............. 223 7.8.4 Operation as input pulse interval measurement ................227 7.8.5 Operation as input signal high-/low-level width measurement ............231 7.8.6 Operation as delay counter ......................
Page 12 CHAPTER 9 12-BIT INTERVAL TIMER ....................292 9.1 Functions of 12-bit Interval Timer ..................... 292 9.2 Configuration of 12-bit Interval Timer ..................292 9.3 Registers Controlling 12-bit Interval Timer................293 9.3.1 Peripheral enable register 0 (PER0) ....................293 9.3.2 Subsystem clock supply mode control register (OSMC) ..............294 9.3.3 Interval timer control register (ITMC) ....................
Page 13 12.3.4 A/D converter mode register 2 (ADM2) ..................328 12.3.5 10-bit A/D conversion result register (ADCR) ................330 12.3.6 8-bit A/D conversion result register (ADCRH) ................331 12.3.7 Analog input channel specification register (ADS) ................ 332 12.3.8 Conversion result comparison upper limit setting register (ADUL) ..........334 12.3.9 Conversion result comparison lower limit setting register (ADLL) ..........
Page 14 13.2.2 Lower 8/9 bits of the serial data register mn (SDRmn) ..............374 13.3 Registers Controlling Serial Array Unit .................. 376 13.3.1 Peripheral enable register 0 (PER0) ..................... 377 13.3.2 Serial clock select register m (SPSm) ..................378 13.3.3 Serial mode register mn (SMRmn) ....................379 13.3.4 Serial communication operation setting register mn (SCRmn) .............
Page 15 13.7.2 Data transmission ......................... 506 13.7.3 Data reception ..........................510 13.7.4 Stop condition generation ......................516 13.7.5 Calculating transfer rate ....................... 517 13.7.6 Procedure for processing errors that occurred during simplified I C (IIC00, IIC20) communication ..........................519 CHAPTER 14 SERIAL INTERFACE IICA ................... 520 14.1 Functions of Serial Interface IICA ...................
Page 16 CHAPTER 15 RF TRANSCEIVER ......................605 15.1 Overview of RF Transceiver ....................606 15.2 Pin Functions ..........................607 15.2.1 Digital pins ............................ 607 15.2.2 Analog pins ........................... 608 15.3 Configuration of RF Transceiver .................... 609 15.3.1 Digital block ..........................610 15.3.2 Interface block ..........................
Page 17 17.1 Functions of DMA Controller ....................640 17.2 Configuration of DMA Controller .................... 641 17.2.1 DMA SFR address register n (DSAn) ................... 641 17.2.2 DMA RAM address register n (DRAn) ..................642 17.2.3 DMA byte count register n (DBCn) ....................643 17.3 Registers Controlling DMA Controller ...................
Page 18 19.3.1 HALT mode ..........................689 19.3.2 STOP mode ..........................694 19.3.3 SNOOZE mode ..........................699 CHAPTER 20 RESET FUNCTION ......................702 20.1 Timing of Reset Operation ...................... 704 20.2 States of Operation During Reset Periods................706 20.3 Register for Confirming Reset Source ................... 708 20.3.1 Reset control flag register (RESF) ....................
Page 19 23.3.5 SFR guard function ........................744 23.3.5.1 Invalid memory access detection control register (IAWCTL) ..........744 23.3.6 Invalid memory access detection function ..................745 23.3.6.1 Invalid memory access detection control register (IAWCTL) ..........746 23.3.7 Frequency detection function ....................... 747 23.3.7.1 Timer input select register 0 (TIS0) ..................
Page 20 26.6 Self-Programming ........................777 26.6.1 Self-programming procedure ......................778 26.6.2 Boot swap function ........................779 26.6.3 Flash shield window function ......................781 26.7 Security Settings ........................782 26.8 Data Flash ..........................784 26.8.1 Data flash overview ........................784 26.8.2 Register controlling data flash memory ..................785 26.8.3 Procedure for accessing data flash memory ................
Page 21 30.5 Current Consumption ......................823 30.5.1 MCU ............................. 823 30.5.2 RF unit ............................828 30.6 AC Characteristics ........................829 30.7 Peripheral Functions Characteristics ..................833 30.7.1 Serial array unit ..........................833 30.7.2 Serial interface IICA ........................858 30.8 Analog Characteristics ......................862 30.8.1 A/D converter characteristics ......................
Page 22: Chapter 1 Outline
R01UH0515EJ0120 RL78/G1D Rev.1.20 RENESAS MCU Dec 16, 2016 CHAPTER 1 OUTLINE The RL78/G1D is a microcomputer incorporating the RL78 CPU core and low power consumption RF transceiver supporting the Bluetooth ver.4.1 (Low Energy Single mode) specifications. 1.1 Features Ultra-low power consumption technology ●...
Page 23 RL78/G1D CHAPTER 1 OUTLINE High-speed on-chip oscillator ● Select from 32 MHz, 24 MHz, 16 MHz, 12 MHz, 8 MHz, 6 MHz, 4 MHz, 3 MHz, 2 MHz, and 1 MHz ● High accuracy: ±1.0 % (V = 1.8 to 3.6 V, T = -20 to +85 °C) Low-speed on-chip oscillator ●...
Page 24 RL78/G1D CHAPTER 1 OUTLINE Others ● On-chip BCD (binary-coded decimal) correction circuit Note Can be selected only in HS (high-speed main) mode ● ROM, RAM capacities Flash ROM Data Flash RL78/G1D 128 KB 8 KB 12 KB R5F11AGG 192 KB 8 KB 16 KB R5F11AGH...
Page 25: List Of Part Numbers
Note For the fields of application, see Figure 1-1 Part Number, Memory Size, and Package of RL78/G1D. Caution The ordering part numbers represent the numbers at the time of publication. For the latest ordering part numbers, refer to the target product page of the Renesas Electronics website. R01UH0515EJ0120 Rev.1.20...
Page 26: Pin Configuration (Top View)
RL78/G1D CHAPTER 1 OUTLINE 1.3 Pin Configuration (Top View) ● 48-pin plastic WQFN (6 × 6 mm, 0.4 mm pitch) <R> 36 35 34 33 32 31 30 29 28 27 26 25 P61/SDAA0 SS_RF DCLIN P60/SCLA0 exposed die pad GPIO2/CLKOUT_RF GPIO3/EXSLK_RF REGC...
Page 27: Pin Identification
RL78/G1D CHAPTER 1 OUTLINE 1.4 Pin Identification ANI0 to ANI3, Analog input PCLBUZ0: Programmable clock output/buzzer ANI16 to ANI19: output ANT: Antenna connection REGC: Regulator capacitance Power supply for RF RFCTLEN: RF control enable DD_RF analog RTC1HZ: Real-time clock correction clock Analog reference voltage (1 Hz) output REFM...
Page 28: Block Diagram
RL78/G1D CHAPTER 1 OUTLINE 1.5 Block Diagram TIMER ARRAY P00 to P03 PORT 0 UNIT (8ch) TI00/P00 PORT 1 P10 to P16 TO00/P01 TI01/TO01/P16 PORT 2 P20 to P23 (TI02/TO02/P15) PORT 3 (TI03/TO03/P14) PORT 4 (TI04/TO04/P13) PORT 6 P60, P61 (TI05/TO05/P12) PORT 7 (TI06/TO06/P11)
Page 29: Outline Of Functions
RL78/G1D CHAPTER 1 OUTLINE 1.6 Outline of Functions Caution This outline describes the functions at the time when Peripheral I/O redirection register (PIOR) is set to 00H. (1/2) Item R5F11AGG R5F11AGH R5F11AGJ Code flash memory 128 KB 192 KB 256 KB Data flash memory 8 KB 8 KB...
Page 30 RL78/G1D CHAPTER 1 OUTLINE Notes 1. This is about 19 KB when the self-programming function is used. When RF is used, this count includes the pins that connect the MCU with the RF transceiver by the user externally on the board. R01UH0515EJ0120 Rev.1.20 Dec 16, 2016...
Page 31 RL78/G1D CHAPTER 1 OUTLINE (2/2) Item R5F11AGG R5F11AGH R5F11AGJ Note 1 Note 2 Timer Timer output 8 channels (PWM outputs: 7 RTC output 1 channel 1 Hz (subsystem clock: f = 32.768 kHz) Note 3 Clock output/buzzer output ● 2.44 kHz, 4.88 kHz, 9.76 kHz, 1.25 MHz, 2.5 MHz, 5 MHz, 10 MHz (Main system clock: f = 20 MHz operation) MAIN...
Page 32: Chapter 2 Connection Between Mcu And Rf Transceiver
Bluetooth Low Energy operation. These pins require initial settings for the appropriate modes and levels using the Bluetooth Low Energy software stack from Renesas before communications with another RF transceiver can start. R01UH0515EJ0120 Rev.1.20 Dec 16, 2016...
Page 33 RL78/G1D CHAPTER 2 CONNECTION BETWEEN MCU AND RF TRANSCEIVER Table 2-1. Internal Pin Connection Pin Name Function Direction MCU unit RF unit RESET_RF Hardware reset signal for the RF unit (baseband unit). When RESET_RF is at MCU → the low level, the RF unit (baseband unit) enters the reset state. RESET_RF RF transceiver is controlled by P05 which is an internal port of the MCU.
Page 34: Communication Interface Between Mcu And Rf Transceiver
After release from the reset state, the following internal pins of the MCU need to be set for output mode (set the port registers and port mode registers to 0) by software. Using the Bluetooth Low Energy software stack from Renesas leads to the appropriate initial settings being made.
Page 35: Operation Clock Of Bluetooth Low Energy
RF slow clock. In the case of square wave input to the EXSLK_RF pin, the Bluetooth Low Energy software stack from Renesas sets up sub-clock output through the PCLBUZ0 pin to provide a square wave for input to EXSLK_RF, so the PCLBUZ0 pin and EXSLK_RF pin must be connected on the user board.
Page 36: Power Configuration
RL78/G1D CHAPTER 2 CONNECTION BETWEEN MCU AND RF TRANSCEIVER 2.5 Power Configuration Power is supplied to both the MCU and the RF unit. The RF unit includes a DC-DC converter. Whether to use the DC- DC converter or not is selectable, so the user is able to select the configuration that suits the user application. The power switched at the DC-DC converter is output to the DCLOUT pin.
Page 37: Chapter 3 Pin Functions
RL78/G1D CHAPTER 3 PIN FUNCTIONS CHAPTER 3 PIN FUNCTIONS 3.1 Pin Functions The relationship between these power supplies and the pins is shown below. Table 3-1. Pin I/O Buffer Power Supplies Power Supply Corresponding Pins ● P00 to P03, P10 to P16, P20 to P23, P30, P40, P60, P61, P120 to P124, P130, P137, P140, and P147 ●...
Page 38 RL78/G1D CHAPTER 3 PIN FUNCTIONS The I/O, buffer, and pull-up resistor settings for each port is also valid for alternate functions. (1/2) Function Name Pin Type After Reset Alternate Function Function 7-1-2 Input port TI00 Port 0. 4-bit I/O port. 8-1-1 TO00 Input/output can be specified in 1-bit units.
Page 39 RL78/G1D CHAPTER 3 PIN FUNCTIONS (2/2) Function Name Pin Type After Reset Alternate Function Function P120 7-3-1 Analog input ANI19 Port 12. port 1-bit I/O port and 4-bit input-only port. For only P120, input/output can be specified. P121 2-2-1 Input Input port For only P120, use of an on-chip pull-up resistor P122...
Page 40: Functions Other Than Port Pins
RL78/G1D CHAPTER 3 PIN FUNCTIONS 3.2 Functions Other than Port Pins (1/2) Function Name Pin Type Function ANI0 4-3-1 Input A/D converter analog input (see Figure 12-44 Analog Input Pin Connection) ANI1 4-3-1 ANI2 4-3-1 ANI3 4-3-1 ANI16 8-3-2 ANI17 7-3-2 ANI18 7-3-1...
Page 41 RL78/G1D CHAPTER 3 PIN FUNCTIONS (2/2) Function Name Pin Type Function TO00 8-1-1 Output Timer output of 16-bit timer 00 TO01 8-1-1 Output Timer output of 16-bit timer 01 TO02 8-1-2 Output Timer output of 16-bit timer 02 TO03 7-1-1 Output Timer output of 16-bit timer 03 TO04...
Page 42 RL78/G1D CHAPTER 3 PIN FUNCTIONS Caution After reset release, the relationships between P40/TOOL0 and the operating mode are as follows. Table 3-2. Relationships Between P40/TOOL0 and Operation Mode After Reset Release P40/TOOL0 Operating Mode Normal operation mode Flash memory programming mode For details, see 26.4 Serial Programming Method.
Page 43: Connection Of Unused Pins
RL78/G1D CHAPTER 3 PIN FUNCTIONS 3.3 Connection of Unused Pins Table 3-3 shows the connections of unused pins. Table 3-3. Connection of Unused Pins (1/2) Pin Name Recommended Connection of Unused Pins P00/TI00 Input: Independently connect to V or V via a resistor.
Page 44 RL78/G1D CHAPTER 3 PIN FUNCTIONS Table 3-3. Connection of Unused Pins (2/2) Pin Name Recommended Connection of Unused Pins <R> GPIO3/EXSLK_RF When the on-chip oscillator is used for RF slow clock: Leave open or connect to P140/PCLBUZ0/INTP6. When the on-chip oscillator is not used for RF slow clock: connect to V SS_RF (When this pin is not in use, it always functions as an input port in the reset state or after released from the reset state.)
Page 45: Block Diagrams Of Pins
RL78/G1D CHAPTER 3 PIN FUNCTIONS 3.4 Block Diagrams of Pins Figures 3-1 to 3-14 show the block diagrams. Figure 3-1. Pin Block Diagram for Pin Type 1-1-1 PORT P-ch Output latch (Pmn) N-ch Figure 3-2. Pin Block Diagram for Pin Type 2-1-1 RESET RESET Figure 3-3.
Page 46 RL78/G1D CHAPTER 3 PIN FUNCTIONS Figure 3-4. Pin Block Diagram for Pin Type 2-2-1 Clock generator OSCSEL/ OSCSELS Alternate function P122/X2/EXCLK/Alternate function P124/XT2/EXCLKS/Alternate function EXCLK, OSCSEL/ EXCLKS, OSCSELS N-ch P-ch Alternate function P121/X1/Alternate function P123/XT1/Alternate function Remark For alternate functions, see 3.1 Port Function. R01UH0515EJ0120 Rev.1.20 Dec 16, 2016...
Page 47 RL78/G1D CHAPTER 3 PIN FUNCTIONS Figure 3-5. Pin Block Diagram for Pin Type 4-3-1 ADPC 0: Analog input ADPC 1: Digital I/O ADPC3 to ADPC0 PORT Output latch (Pmn) P-ch N-ch PM register (PMmn) P-ch A/D converter N-ch R01UH0515EJ0120 Rev.1.20 Dec 16, 2016...
Page 48 RL78/G1D CHAPTER 3 PIN FUNCTIONS Figure 3-6. Pin Block Diagram for Pin Type 7-1-1 PU register P-ch (PUmn) Alternate function PORT Output latch (Pmn) P-ch PM register N-ch (PMmn) Alternate function Remark For alternate functions, see 3.1 Port Function. R01UH0515EJ0120 Rev.1.20 Dec 16, 2016...
Page 49 RL78/G1D CHAPTER 3 PIN FUNCTIONS Figure 3-7. Pin Block Diagram for Pin Type 7-1-2 PU register P-ch (PUmn) Alternate function PORT Output latch (Pmn) P-ch PM register N-ch (PMmn) POM register (POMmn) Alternate function (SAU) Alternate function (other than SAU) Remarks 1.
Page 50 RL78/G1D CHAPTER 3 PIN FUNCTIONS <R> Figure 3-8. Pin Block Diagram for Pin Type 7-3-1 PU register P-ch (PUmn) PMC register (PMCmn) Alternate function PORT Output latch (Pmn) P-ch N-ch PM register (PMmn) Alternate function (SAU) Alternate function (other than SAU) P-ch A/D converter N-ch...
Page 51 RL78/G1D CHAPTER 3 PIN FUNCTIONS Figure 3-9. Pin Block Diagram for Pin Type 7-3-2 PU register P-ch (PUmn) PMC register (PMCmn) Alternate function PORT Output latch (Pmn) P-ch N-ch PM register (PMmn) Alternate function (SAU) Alternate function (other than SAU) P-ch A/D converter N-ch...
Page 52 RL78/G1D CHAPTER 3 PIN FUNCTIONS Figure 3-10. Pin Block Diagram for Pin Type 8-1-1 PU register P-ch (PUmn) PIM register (PIMmn) Alternate function CMOS PORT Output latch (Pmn) P-ch PM register N-ch (PMmn) Alternate function (SAU) Alternate function (other than SAU) Remarks 1.
Page 53 RL78/G1D CHAPTER 3 PIN FUNCTIONS Figure 3-11. Pin Block Diagram for Pin Type 8-1-2 PU register P-ch (PUmn) PIM register (PIMmn) Alternate function CMOS PORT Output latch (Pmn) P-ch PM register N-ch (PMmn) POM register (POMmn) Alternate function (SAU) Alternate function (other than SAU) Remarks 1.
Page 54 RL78/G1D CHAPTER 3 PIN FUNCTIONS Figure 3-12. Pin Block Diagram for Pin Type 8-3-2 PU register (PUmn) P-ch PIM register (PIMmn) PMC register (PMCmn) Alternate function CMOS PORT Output latch (Pmn) P-ch N-ch PM register (PMmn) Alternate function (SAU) Alternate function (other than SAU) P-ch A/D converter...
Page 55 RL78/G1D CHAPTER 3 PIN FUNCTIONS Figure 3-13. Pin Block Diagram for Pin Type 12-1-1 Alternate function PORT Output latch (Pmn) N-ch PM register (PMmn) Alternate function (SAU) Alternate function (other than SAU) Remarks 1. For alternate functions, see 3.1 Port Function. 2.
Page 56 RL78/G1D CHAPTER 3 PIN FUNCTIONS Figure 3-14. Pin Block Diagram for Pin Type R-11 INOUT 3 V buffer Figure 3-15. Pin Block Diagram for Pin Type R-12 Output enable INOUT Data Data Data Input 3 V buffer Input enable R01UH0515EJ0120 Rev.1.20 Dec 16, 2016...
Page 57: Chapter 4 Cpu Architecture
RL78/G1D CHAPTER 4 CPU ARCHITECTURE CHAPTER 4 CPU ARCHITECTURE 4.1 Memory Space Products in the RL78/G1D can access a 1 MB address space. Figures 4-1 to 4-3 show the memory maps. R01UH0515EJ0120 Rev.1.20 Dec 16, 2016...
Page 58 RL78/G1D CHAPTER 4 CPU ARCHITECTURE Figure 4-1. Memory Map (R5F11AGG) 1 F F F F H F F F F F H Special function register (SFR) 256 bytes F F F 0 0 H F F E F F H General-purpose register 32 bytes F F E E 0 H...
Page 59 RL78/G1D CHAPTER 4 CPU ARCHITECTURE Figure 4-2. Memory Map (R5F11AGH) 2 F F F F H F F F F F H Special function register (SFR) 256 bytes F F F 0 0 H F F E F F H General-purpose register 32 bytes F F E E 0 H...
Page 60 RL78/G1D CHAPTER 4 CPU ARCHITECTURE Figure 4-3. Memory Map (R5F11AGJ) F F F F F H 3 F F F F H Special function register (SFR) 256 bytes F F F 0 0 H F F E F F H General-purpose register 32 bytes F F E E 0 H...
Page 61 RL78/G1D CHAPTER 4 CPU ARCHITECTURE Correspondence between the address values and block numbers in the flash memory are shown below. Table 4-1. Correspondence Between Address Values and Block Numbers in Flash Memory (1/2) Address Value Block Address Value Block Address Value Block Address Value Block...
Page 62 RL78/G1D CHAPTER 4 CPU ARCHITECTURE Table 4-1. Correspondence Between Address Values and Block Numbers in Flash Memory (2/2) Block Block Block Block Address Value Address Value Address Value Address Value Number Number Number Number 20000H to 203FFH 28000H to 283FFH 30000H to 303FFH 38000H to 383FFH 20400H to 207FFH...
Page 63: Internal Program Memory Space
RL78/G1D CHAPTER 4 CPU ARCHITECTURE 4.1.1 Internal program memory space The internal program memory space stores the program and table data. The RL78/G1D products incorporate internal ROM (flash memory), as shown below. Table 4-2. Internal ROM Capacity Part Number Internal ROM Structure Capacity R5F11AGG...
Page 64 RL78/G1D CHAPTER 4 CPU ARCHITECTURE Table 4-3. Vector Table Vector Table Address Interrupt Source 0000H RESET, POR, LVD, WDT, TRAP, IAW, RPE 0004H INTWDTI 0006H INTLVI 0008H INTP0 000EH INTP3 0012H INTP5 0014H INTCSI20/INTIIC20 0016H INTCSI21 0018H INTTM11H 001AH INTDMA0 001CH INTDMA1 001EH...
Page 65 RL78/G1D CHAPTER 4 CPU ARCHITECTURE (2) CALLT instruction table area The 64-byte area 00080H to 000BFH can store the subroutine entry address of a 2-byte call instruction (CALLT). Set the subroutine entry address to a value in a range of 00000H to 0FFFFH (because an address code is of 2 bytes). To use the boot swap function, set a CALLT instruction table also at 01080H to 010BFH.
Page 66: Mirror Area
RL78/G1D CHAPTER 4 CPU ARCHITECTURE 4.1.2 Mirror area The RL78/G1D mirrors the code flash area of 00000H to 0FFFFH or 10000H to 1FFFFH, to F0000H to FFFFFH (the code flash area to be mirrored is set by the processor mode control register (PMC)). By reading data from F0000H to FFFFFH, an instruction that does not have the ES register as an operand can be used, and thus the contents of the code flash can be read with the shorter code.
Page 67 RL78/G1D CHAPTER 4 CPU ARCHITECTURE ● Processor mode control register (PMC) This register sets the flash memory space for mirroring to area from F0000H to FFFFFH. The PMC register can be set by a 1-bit or 8-bit memory manipulation instruction. Reset signal generation sets this register to 00H.
Page 68: Internal Data Memory Space
RL78/G1D CHAPTER 4 CPU ARCHITECTURE 4.1.3 Internal data memory space The RL78/G1D products incorporate the following RAMs. Table 4-4. Internal RAM Capacity Part Number Internal RAM R5F11AGG 12288 × 8 bits (FCF00H to FFEFFH) R5F11AGH 16384 × 8 bits (FBF00H to FFEFFH) R5F11AGJ 20480 ×...
Page 69: Data Memory Addressing
RL78/G1D CHAPTER 4 CPU ARCHITECTURE 4.1.6 Data memory addressing Addressing refers to the method of specifying the address of the instruction to be executed next or the address of the register or memory relevant to the execution of instructions. Several addressing modes are provided for addressing the memory relevant to the execution of instructions for the RL78/G1D, based on operability and other considerations.
Page 70 RL78/G1D CHAPTER 4 CPU ARCHITECTURE Figure 4-6. Correspondence Between Data Memory and Addressing (R5F11AGH) FFFFFH SFR addressing Special function register (SFR) FFF20H 256 bytes FFF1FH FFF00H Short direct FFEFFH General-purpose register addressing Register addressing 32 bytes FFEE0H FFEDFH FFE20H Note1 FFE1FH 16 KB FBF00H...
Page 71 RL78/G1D CHAPTER 4 CPU ARCHITECTURE Figure 4-7. Correspondence Between Data Memory and Addressing (R5F11AGJ) F F F F F H Special function register (SFR) SFR addressing F F F 2 0 H F F F 1 F H 256 bytes F F F 0 0 H Short direct F F E F F H...
Page 72: Processor Registers
RL78/G1D CHAPTER 4 CPU ARCHITECTURE 4.2 Processor Registers The RL78/G1D products incorporate the following processor registers. 4.2.1 Control registers The control registers control the program sequence, statuses and stack memory. The control registers consist of a program counter (PC), a program status word (PSW) and a stack pointer (SP). (1) Program counter (PC) The program counter is a 20-bit register that holds the address information of the next program to be executed.
Page 73 RL78/G1D CHAPTER 4 CPU ARCHITECTURE (d) Auxiliary carry flag (AC) If the operation result has a carry from bit 3 or a borrow at bit 3, this flag is set (1). It is reset (0) in all other cases. (e) In-service priority flags (ISP1, ISP0) This flag manages the priority of acknowledgeable maskable vectored interrupts.
Page 74: General-Purpose Registers
RL78/G1D CHAPTER 4 CPU ARCHITECTURE 4.2.2 General-purpose registers General-purpose registers are mapped at particular addresses (FFEE0H to FFEFFH) of the data memory. The general- purpose registers consists of 4 banks, each bank consisting of eight 8-bit registers (X, A, C, B, E, D, L, and H). Each register can be used as an 8-bit register, and two 8-bit registers can also be used in a pair as a 16-bit register (AX, BC, DE, and HL).
Page 75: And Cs Registers
RL78/G1D CHAPTER 4 CPU ARCHITECTURE 4.2.3 ES and CS registers The ES register and CS register are used to specify the higher address for data access and when a branch instruction is executed (register direct addressing), respectively. The default value of the ES register after reset is 0FH, and that of the CS register is 00H. Figure 4-12.
Page 76: Special Function Registers (Sfrs)
RL78/G1D CHAPTER 4 CPU ARCHITECTURE 4.2.4 Special function registers (SFRs) Unlike a general-purpose register, each SFR has a special function. SFRs are allocated to the FFF00H to FFFFFH area. SFRs can be manipulated like general-purpose registers, using operation, transfer, and bit manipulation instructions. The manipulable bit units, 1, 8, and 16, depend on the SFR type.
Page 77 RL78/G1D CHAPTER 4 CPU ARCHITECTURE Table 4-5. SFR List (1/4) Address Special Function Register (SFR) Name Symbol Manipulable Bit Range After Reset 1-bit 8-bit 16-bit FFF00H Port register 0 –   FFF01H Port register 1 –   FFF02H Port register 2 –...
Page 78 RL78/G1D CHAPTER 4 CPU ARCHITECTURE Table 4-5. SFR List (2/4) Address Special Function Register (SFR) Name Symbol Manipulable Bit Range After Reset 1-bit 8-bit 16-bit FFF38H External interrupt rising edge enable EGP0 –   register 0 FFF39H External interrupt falling edge enable EGN0 –...
Page 79 RL78/G1D CHAPTER 4 CPU ARCHITECTURE Table 4-5. SFR List (3/4) Address Special Function Register (SFR) Name Symbol Manipulable Bit Range After Reset 1-bit 8-bit 16-bit Note 1 FFF94H Hour count register HOUR – –  FFF95H Week count register WEEK –...
Page 80 RL78/G1D CHAPTER 4 CPU ARCHITECTURE Notes 1. The value of this register is 00H if the AMPM bit (bit 3 of real-time clock control register 0 (RTCC0)) is set to 1 after reset. 2. The reset values of the registers vary depending on the reset source as shown below. Reset Source RESET Input Reset by...
Page 81 RL78/G1D CHAPTER 4 CPU ARCHITECTURE Table 4-5. SFR List (4/4) Address Special Function Register (SFR) Name Symbol Manipulable Bit Range After Reset 1-bit 8-bit 16-bit FFFBAH DMA mode control register 0 DMC0 –   FFFBBH DMA mode control register 1 DMC1 –...
Page 82: Extended Special Function Registers (2Nd Sfrs: 2Nd Special Function Registers)
RL78/G1D CHAPTER 4 CPU ARCHITECTURE 4.2.5 Extended special function registers (2nd SFRs: 2nd Special Function Registers) Unlike a general-purpose register, each extended SFR (2nd SFR) has a special function. Extended SFRs are allocated to the F0000H to F07FFH area. SFRs other than those in the SFR area (FFF00H to FFFFFH) are allocated to this area.
Page 83 RL78/G1D CHAPTER 4 CPU ARCHITECTURE Table 4-6. Extended SFR (2nd SFR) List (1/5) Address Special Function Register (SFR) Name Symbol Manipulable Bit Range After Reset 1-bit 8-bit 16-bit F0010H A/D converter mode register 2 ADM2 –   F0011H Conversion result comparison upper ADUL –...
Page 84 RL78/G1D CHAPTER 4 CPU ARCHITECTURE Table 4-6. Extended SFR (2nd SFR) List (2/5) Address Special Function Register (SFR) Name Symbol Manipulable Bit Range After Reset 1-bit 8-bit 16-bit F0100H Serial status register 00 SSR00L SSR00 – 0000H   F0101H –...
Page 85 RL78/G1D CHAPTER 4 CPU ARCHITECTURE Table 4-6. Extended SFR (2nd SFR) List (3/5) Address Special Function Register (SFR) Name Symbol Manipulable Bit Range After Reset 1-bit 8-bit 16-bit F0128H Serial output register 0 – – 0F0FH  F0129H F012AH Serial output enable register 0 SOE0L SOE0 0000H...
Page 86 RL78/G1D CHAPTER 4 CPU ARCHITECTURE Table 4-6. Extended SFR (2nd SFR) List (4/5) Address Special Function Register (SFR) Name Symbol Manipulable Bit Range After Reset 1-bit 8-bit 16-bit F0188H Timer counter register 04 TCR04 – – FFFFH  F0189H F018AH Timer counter register 05 TCR05 –...
Page 87 RL78/G1D CHAPTER 4 CPU ARCHITECTURE Table 4-6. Extended SFR (2nd SFR) List (5/5) Address Special Function Register (SFR) Name Symbol Manipulable Bit Range After Reset 1-bit 8-bit 16-bit F01B0H Timer channel enable status register 0 TE0L 0000H    F01B1H –...
Page 88: Instruction Address Addressing
RL78/G1D CHAPTER 4 CPU ARCHITECTURE 4.3 Instruction Address Addressing 4.3.1 Relative addressing [Function] Relative addressing stores in the program counter (PC) the result of adding a displacement value included in the instruction word (signed complement data: –128 to +127 or –32768 to +32767) to the program counter (PC)’s value (the start address of the next instruction), and specifies the program address to be used as the branch destination.
Page 89: Register Direct Addressing
RL78/G1D CHAPTER 4 CPU ARCHITECTURE 4.3.3 Table indirect addressing [Function] Table indirect addressing specifies a table address in the CALLT table area (0080H to 00BFH) with the 5-bit immediate data in the instruction word, stores the contents at that table address and the next address in the program counter (PC) as 16-bit data, and specifies the program address.
Page 90: Addressing For Processing Data Addresses
RL78/G1D CHAPTER 4 CPU ARCHITECTURE 4.4 Addressing for Processing Data Addresses 4.4.1 Implied addressing [Function] Instructions for accessing registers (such as accumulators) that have special functions are directly specified with the instruction word, without using any register specification field in the instruction word. [Operand format] Implied addressing can be applied only to MULU X.
Page 91: Direct Addressing
RL78/G1D CHAPTER 4 CPU ARCHITECTURE 4.4.3 Direct addressing [Function] Direct addressing uses immediate data in the instruction word as an operand address to directly specify the target address. [Operand format] Identifier Description !addr16 Label or 16-bit immediate data (only the space from F0000H to FFFFFH is specifiable) ES:!addr16 Label or 16-bit immediate data (higher 4-bit addresses are specified by the ES register) Figure 4-21.
Page 92: Short Direct Addressing
RL78/G1D CHAPTER 4 CPU ARCHITECTURE 4.4.4 Short direct addressing [Function] Short direct addressing directly specifies the target addresses using 8-bit data in the instruction word. This type of addressing is applied only to the space from FFE20H to FFF1FH. [Operand format] Identifier Description SADDR...
Page 93: Sfr Addressing
RL78/G1D CHAPTER 4 CPU ARCHITECTURE 4.4.5 SFR addressing [Function] SFR addressing directly specifies the target SFR addresses using 8-bit data in the instruction word. This type of addressing is applied only to the space from FFF00H to FFFFFH. [Operand format] Identifier Description SFR name...
Page 94: Register Indirect Addressing
RL78/G1D CHAPTER 4 CPU ARCHITECTURE 4.4.6 Register indirect addressing [Function] Register indirect addressing directly specifies the target addresses using the contents of the register pair specified with the instruction word as an operand address. [Operand format] Identifier Description – [DE], [HL] (only the space from F0000H to FFFFFH is specifiable) –...
Page 95: Based Addressing
RL78/G1D CHAPTER 4 CPU ARCHITECTURE 4.4.7 Based addressing [Function] Based addressing uses the contents of a register pair specified with the instruction word or 16-bit immediate data as a base address, and 8-bit immediate data or 16-bit immediate data as offset data. The sum of these values is used to specify the target address.
Page 96 RL78/G1D CHAPTER 4 CPU ARCHITECTURE Figure 4-28. Example of [HL + byte], [DE + byte] [HL + byte], [DE + byte] <1> <2> <1> <2> FFFFFH Instruction code Target OP-code Target memory array <2> Offset of data <2> byte <1> Address of Other data in an array...
Page 97 RL78/G1D CHAPTER 4 CPU ARCHITECTURE Figure 4-30. Example of word[BC] word [BC] FFFFFH <1> <2> Array of Target memory Instruction code <2> word-sized <2> Offset data OP-code rp(BC) Address of a word Low Addr. <1> within an array <1> F0000H High Addr.
Page 98 RL78/G1D CHAPTER 4 CPU ARCHITECTURE Figure 4-32. Example of ES:word[B], ES:word[C] ES: word [B], ES: word [C] <1> <2> <3> <1> <2> <3> XFFFFH <3> Instruction code Array of <3> Target memory Offset word-sized OP-code data r(B/C) <2> Low Addr. Address of a word within an array <2>...
Page 99: Based Indexed Addressing
RL78/G1D CHAPTER 4 CPU ARCHITECTURE 4.4.8 Based indexed addressing [Function] Based indexed addressing uses the contents of a register pair specified with the instruction word as the base address, and the content of the B register or C register similarly specified with the instruction word as offset address. The sum of these values is used to specify the target address.
Page 100: Stack Addressing
RL78/G1D CHAPTER 4 CPU ARCHITECTURE 4.4.9 Stack addressing [Function] The stack area is indirectly addressed with the stack pointer (SP) values. This addressing is automatically employed when the PUSH, POP, subroutine call, and return instructions are executed or the register is saved/restored upon generation of an interrupt request.
Page 101 RL78/G1D CHAPTER 4 CPU ARCHITECTURE Figure 4-37. Example of POP POP rp <1> <2> SP+ 2 <1> (SP+1) SP+ 1 Stack Instruction code area (SP) <2> OP-code F0000H Stack addressing is specified <1>. The contents of addresses SP and SP + 1 are stored in the lower-order and higher-order bytes of the pair of registers indicated by rp <2>, respectively.
Page 102 RL78/G1D CHAPTER 4 CPU ARCHITECTURE Figure 4-39. Example of RET <1> SP+4 <1> (SP+3) SP+3 Instruction code Stack SP+2 (SP+2) OP-code area (SP+1) SP+1 <3> (SP) <2> F0000H Stack addressing is specified <1>. The contents of addresses SP, SP + 1, and SP + 2 are stored in PC bits 7 to 0, 15 to 8, and 19 to 16, respectively <2>.
Page 103 RL78/G1D CHAPTER 4 CPU ARCHITECTURE Figure 4-41. Example of RETI, RETB RETI, RETB <1> SP+4 <1> SP+3 (SP+3) Instruction code (SP+2) SP+2 Stack OP-code (SP+1) area SP+1 <3> (SP) <2> F0000H Stack addressing is specified <1>. Memory The contents of addresses SP, SP + 1, SP + 2, and SP + 3 are stored in PC bits 7 to 0, 15 to 8, 19 to 16, and the PSW, respectively <2>.
Page 104: Chapter 5 Port Functions
RL78/G1D CHAPTER 5 PORT FUNCTIONS CHAPTER 5 PORT FUNCTIONS 5.1 Port Functions The RL78/G1D microcontrollers are provided with digital I/O ports, which enable variety of control operations. In addition to the function as digital I/O ports, these ports have several alternate functions. For details of the alternate functions, see CHAPTER 3 PIN FUNCTIONS.
Page 105: Port Configuration
RL78/G1D CHAPTER 5 PORT FUNCTIONS 5.2 Port Configuration Ports include the following hardware. Table 5-1. Port Configuration Item Configuration Control registers Port mode registers (PM0 to PM7, PM12, PM14) Port registers (P0 to P7, P12 to P14) Pull-up resistor option registers (PU0, PU1, PU3, PU4, PU12, PU14) Port input mode registers (PIM0, PIM1) Port output mode registers (POM0, POM1) Port mode control registers (PMC0, PMC12, and PMC14)
Page 106: Port 0
RL78/G1D CHAPTER 5 PORT FUNCTIONS 5.2.1 Port 0 Port 0 is an I/O port with an output latch. Port 0 can be set to input mode or output mode in 1-bit units using the port mode register 0 (PM0). When the P00 to P03 pins are used as an input port, use of an on-chip pull-up resistor can be specified in 1-bit units by the pull-up resistor option register 0 (PU0).
Page 107: Port 2
RL78/G1D CHAPTER 5 PORT FUNCTIONS 5.2.3 Port 2 Port 2 is an I/O port with an output latch. Port 2 can be set to input mode or output mode in 1-bit units using the port mode register 2 (PM2). This port can also be used for A/D converter analog input and reference voltage input (+ side and - side). To use P20/ANI0 to P23/ANI3 as digital input/output pins, set them to digital I/O mode by using the A/D port configuration register (ADPC).
Page 108: Port 14
GPIO port is an I/O port with an output latch. For GPIO port, the mode setting and I/O can be specified via API of Renesas Bluetooth Low Energy protocol stack. This port can also be used for external PA/LNA control output, clock output for RF block, and RF external clock I/O.
Page 109: Registers Controlling Port Function
RL78/G1D CHAPTER 5 PORT FUNCTIONS 5.3 Registers Controlling Port Function Port functions are controlled by the following registers. ● Port mode registers (PMxx) ● Port registers (Pxx) ● Pull-up resistor option registers (PUxx) ● Port input mode registers (PIMxx) ● Port output mode registers (POMxx) ●...
Page 110 RL78/G1D CHAPTER 5 PORT FUNCTIONS Table 5-3. PMxx, Pxx, PUxx, PIMxx, POMxx, PMCxx registers and the bits (2/1) Port Bit name PMxx PUxx PIMxx POMxx PMCxx register register register register register register Port 0 PM00 PU00 – POM00 – PM01 PU01 PIM01 –...
Page 111 RL78/G1D CHAPTER 5 PORT FUNCTIONS Table 5-3. PMxx, Pxx, PUxx, PIMxx, POMxx, PMCxx registers and the bits (2/2) Port Bit name PMxx PUxx PIMxx POMxx PMCxx register register register register register register Note Note Port 7 PM70 – – – –...
Page 112: Port Mode Registers (Pmxx)
RL78/G1D CHAPTER 5 PORT FUNCTIONS 5.3.1 Port mode registers (PMxx) These registers specify input or output mode for the port in 1-bit units. These registers can be set by a 1-bit or 8-bit memory manipulation instruction. Reset signal generation sets these registers to FFH. When port pins are used as alternate-function pins, set the port mode register by referencing 5.5 Settings of Port Related Register When Using Alternate Function.
Page 113 RL78/G1D CHAPTER 5 PORT FUNCTIONS Figure 5-1. Format of Port Mode Registers (2/2) Address: FFF2CH After reset: FFH Symbol Note 1 PM12 PM120 Address: FFF2EH After reset: FFH Symbol Note 2 Note 2 PM14 PM147 PM146 PM141 PM140 PMmn Pmn pin I/O mode selection (m = 0 to 7, 12, 14; n = 0 to 7) Output mode (output buffer on) Input mode (output buffer off) Notes 1.
Page 114: Port Registers (Pxx)
RL78/G1D CHAPTER 5 PORT FUNCTIONS 5.3.2 Port registers (Pxx) These registers set the output latch value of a port. If the data is read in the input mode, the pin level is read. If it is read in the output mode, the output latch value is Note read These registers can be set by a 1-bit or 8-bit memory manipulation instruction.
Page 115 RL78/G1D CHAPTER 5 PORT FUNCTIONS Figure 5-2. Format of Port Register Symbol Address After reset Note 4 Note 4 Note 3 FFF00H 00H (output latch) R/W Note 3 FFF01H 00H (output latch) R/W FFF02H 00H (output latch) R/W Note 3 FFF03H 00H (output latch) R/W Note 3...
Page 116: Pull-Up Resistor Option Registers (Puxx)
RL78/G1D CHAPTER 5 PORT FUNCTIONS 5.3.3 Pull-up resistor option registers (PUxx) These registers specify whether the on-chip pull-up resistors are to be used or not. On-chip pull-up resistors can be used in 1-bit units only for the bits set to both normal output mode (POMmn = 0) and input mode (PMmn = 1) for the pins to which the use of an on-chip pull-up resistor has been specified in these registers.
Page 117: Port Input Mode Registers (Pimxx)
RL78/G1D CHAPTER 5 PORT FUNCTIONS 5.3.4 Port input mode registers (PIMxx) These registers set the input buffer in 1-bit units. TTL input buffer can be selected during serial communication with an external device of the different potential. Port input mode registers can be set by a 1-bit or 8-bit memory manipulation instruction. Reset signal generation clears these registers to 00H.
Page 118: Port Output Mode Registers (Pomxx)
RL78/G1D CHAPTER 5 PORT FUNCTIONS 5.3.5 Port output mode registers (POMxx) These registers set the output mode in 1-bit units. N-ch open drain output (V tolerance) mode can be selected during serial communication with an external device of the different potential, and for the SDA00 and SDA20 pins during simplified I C communication with an external device of the same potential.
Page 119: Port Mode Control Registers (Pmcxx)
RL78/G1D CHAPTER 5 PORT FUNCTIONS 5.3.6 Port mode control registers (PMCxx) These registers set the digital I/O/analog input in 1-bit units. These registers can be set by a 1-bit or 8-bit memory manipulation instruction. Reset signal generation clears these registers to FFH. Figure 5-6.
Page 120: A/D Port Configuration Register (Adpc)
RL78/G1D CHAPTER 5 PORT FUNCTIONS 5.3.7 A/D port configuration register (ADPC) This register switches the ANI0/P20 to ANI3/P23 pins to digital I/Os of port or analog input of A/D converter. The ADPC register can be set by an 8-bit memory manipulation instruction. Reset signal generation sets this register to 00H.
Page 121: Peripheral I/O Redirection Register (Pior)
RL78/G1D CHAPTER 5 PORT FUNCTIONS 5.3.8 Peripheral I/O redirection register (PIOR) This register is used to specify whether to enable or disable the peripheral I/O redirect function. This function is used to switch ports to which alternate functions are assigned. Use the PIOR register to assign a port to the function to redirect and enable the function.
Page 122: Port Function Operations
RL78/G1D CHAPTER 5 PORT FUNCTIONS 5.4 Port Function Operations Port operations differ depending on whether the input or output mode is set, as shown below. 5.4.1 Writing to I/O port (1) Output mode A value is written to the output latch by a transfer instruction, and the output latch contents are output from the pin. Once data is written to the output latch, it is retained until data is written to the output latch again.
Page 123: Handling Different Potential (1.8 V, 2.5 V) By Using Evdd ≤ Vdd
RL78/G1D CHAPTER 5 PORT FUNCTIONS 5.4.4 Handling different potential (1.8 V, 2.5 V) by using EV ≤ When connecting an external device operating on a different potential (1.8 V, 2.5 V), it is possible to connect the I/O pins of general ports. 5.4.5 Handling different potential (1.8 V, 2.5 V) by using I/O buffers It is possible to connect an external device operating on a different potential (1.8 V or 2.5 V) by switching I/O buffers with the port input mode register (PIMxx) and port output mode register (POMxx).
Page 124 RL78/G1D CHAPTER 5 PORT FUNCTIONS (2) Setting procedure when using output pins of UART0, UART1, CSI00, and CSI20 functions in N-ch open-drain output mode In case of UART0: In case of UART1: In case of CSI00: P10, P12 In case of CSI20: P13, P15 <1>...
Page 125: Register Settings When Using Alternate Function
RL78/G1D CHAPTER 5 PORT FUNCTIONS 5.5 Register Settings When Using Alternate Function 5.5.1 Basic concept when using alternate function In the beginning, for a pin also assigned to be used for analog input, use the ADPC register or port mode control register (PMCxx) to specify whether to use the pin for analog input or digital input/output.
Page 126: Register Settings For Alternate Function Whose Output Function Is Not Used
RL78/G1D CHAPTER 5 PORT FUNCTIONS Table 5-4. Concept of Basic Settings Output Settings of Unused Alternate Function Output Function of Used Pin Output Function for Port Output Function for SAU Output Function for other than SAU Output function for port –...
Page 127: Register Setting Examples For Used Port And Alternate Functions
RL78/G1D CHAPTER 5 PORT FUNCTIONS 5.5.3 Register setting examples for used port and alternate functions Register setting examples for used port and alternate functions are shown in Table 5-5. The registers used to control the port functions should be set as shown in Table 5-5. See the following remark for legends used in Table 5-5. Remark –: Not supported ×:...
Page 128 RL78/G1D CHAPTER 5 PORT FUNCTIONS Table 5-5. Setting Examples of Registers and Output Latches When Using Alternate Function (2/6) Pin Name Used Function PIORx POMxx PMCxx PMxx Alternate Function Output Function SAU Output Other than Name Function Input – × –...
Page 129 RL78/G1D CHAPTER 5 PORT FUNCTIONS Table 5-5. Setting Examples of Registers and Output Latches When Using Alternate Function (3/6) Pin Name Used Function ADPC PDM2 PMxx Function Name Input ADPC = 01H × × Output ADPC = 01H × ANI0 Analog input ADPC = 00x0xx0x,...
Page 130 RL78/G1D CHAPTER 5 PORT FUNCTIONS Table 5-5. Setting Examples of Registers and Output Latches When Using Alternate Function (4/6) Pin Name Used Function PIORx POMxx PMCxx PMxx Alternate Function Output Function SAU Output Other than Name Function Input – – –...
Page 131 RL78/G1D CHAPTER 5 PORT FUNCTIONS Table 5-5. Setting Examples of Registers and Output Latches When Using Alternate Function (6/6) Pin Name Used Function PIORx POMxx PMCxx PMxx Alternate Function Output Function SAU Output Other than Name Function P130 P130 Output –...
Page 132: Cautions When Using Port Function
RL78/G1D CHAPTER 5 PORT FUNCTIONS 5.6 Cautions When Using Port Function 5.6.1 Cautions on 1-bit manipulation instruction for port register n (Pn) When a 1-bit manipulation instruction is executed on a port that provides both input and output functions, the output latch value of an input port that is not subject to manipulation may be written in addition to the targeted bit.
Page 133: Notes On Specifying The Pin Settings
RL78/G1D CHAPTER 5 PORT FUNCTIONS 5.6.2 Notes on specifying the pin settings If the output function of an alternate function is assigned to a pin that is also used as an output pin, the output of the unused alternate function must be set to its initial state so as to prevent conflicting outputs. This also applies to the functions assigned by using the peripheral I/O redirection register (PIOR).
Page 134: Chapter 6 Clock Generator
RL78/G1D CHAPTER 6 CLOCK GENERATOR CHAPTER 6 CLOCK GENERATOR 6.1 Functions of Clock Generator The clock generator generates the clock to be supplied to the CPU and peripheral hardware. The following three kinds of system clocks and clock oscillators are selectable. (1) Main system clock <1>...
Page 135 (4) RF transceiver reference clock This circuit oscillates a clock of f = 32 MHz by connecting a resonator to the XTAL1_RF and XTAL2_RF pins. This oscillation control is set with Renesas Bluetooth Low Energy protocol stack. Remark f X1 clock oscillation frequency...
Page 136: Configuration Of Clock Generator
RL78/G1D CHAPTER 6 CLOCK GENERATOR 6.2 Configuration of Clock Generator The clock generator includes the following hardware. Table 6-1. Configuration of Clock Generator Item Configuration Control registers Clock operation mode control register (CMC) System clock control register (CKC) Clock operation status control register (CSC) Oscillation stabilization time counter status register (OSTC) Oscillation stabilization time select register (OSTS) Peripheral enable register 0 (PER0)
Page 137 RL78/G1D CHAPTER 6 CLOCK GENERATOR R01UH0515EJ0120 Rev.1.20 Dec 16, 2016...
Page 138: Registers Controlling Clock Generator
RL78/G1D CHAPTER 6 CLOCK GENERATOR Remark f X1 clock oscillation frequency High-speed on-chip oscillator clock frequency External main system clock frequency High-speed system clock frequency : Main system clock frequency MAIN XT1 clock oscillation frequency External subsystem clock frequency : Subsystem clock frequency CPU/peripheral hardware clock frequency Low-speed on-chip oscillator clock frequency 6.3 Registers Controlling Clock Generator...
Page 139 RL78/G1D CHAPTER 6 CLOCK GENERATOR Figure 6-2. Format of Clock Operation Mode Control Register (CMC) Address: FFFA0H After reset: 00H Symbol EXCLK OSCSEL EXCLKS OSCSELS AMPHS1 AMPHS0 AMPH EXCLK OSCSEL High-speed system clock X1/P121 pin X2/EXCLK/P122 pin pin operation mode Input port mode Input port X1 oscillation mode...
Page 140 RL78/G1D CHAPTER 6 CLOCK GENERATOR Cautions 7. The XT1 oscillator is a circuit with low amplification in order to achieve low-power consumption. Note the following points when designing the circuit. ● Pins and circuit boards include parasitic capacitance. Therefore, perform oscillation evaluation using a circuit board to be actually used and confirm that there are no problems.
Page 141: System Clock Control Register (Ckc)
RL78/G1D CHAPTER 6 CLOCK GENERATOR 6.3.2 System clock control register (CKC) This register is used to select a CPU/peripheral hardware clock and a main system clock. The CKC register can be set by a 1-bit or 8-bit memory manipulation instruction. Reset signal generation sets this register to 00H.
Page 142: Clock Operation Status Control Register (Csc)
RL78/G1D CHAPTER 6 CLOCK GENERATOR 6.3.3 Clock operation status control register (CSC) This register is used to control the operations of the high-speed system clock, high-speed on-chip oscillator clock, and subsystem clock (except the low-speed on-chip oscillator clock). The CSC register can be set by a 1-bit or 8-bit memory manipulation instruction. Reset signal generation sets this register to C0H.
Page 143: Oscillation Stabilization Time Counter Status Register (Ostc)
RL78/G1D CHAPTER 6 CLOCK GENERATOR Table 6-2. Stopping Clock Method Clock Condition Before Stopping Clock Setting of CSC (Invalidating External Clock Input) Register Flags CPU and peripheral hardware clocks operate with a clock X1 clock MSTOP = 1 other than the high-speed system clock. External main system (CLS = 0 and MCS = 0, or CLS = 1) clock...
Page 144 RL78/G1D CHAPTER 6 CLOCK GENERATOR Figure 6-5. Format of Oscillation Stabilization Time Counter Status Register (OSTC) Address: FFFA2H After reset: 00H Symbol OSTC MOST MOST MOST MOST MOST MOST MOST MOST MOST MOST MOST MOST MOST MOST MOST MOST Oscillation stabilization time status = 10 MHz = 20 MHz max.
Page 145: Oscillation Stabilization Time Select Register (Osts)
RL78/G1D CHAPTER 6 CLOCK GENERATOR 6.3.5 Oscillation stabilization time select register (OSTS) This register is used to select the X1 clock oscillation stabilization wait time. When the X1 clock is made to oscillate by clearing the MSTOP bit to start the X1 oscillation circuit operating, actual operation is automatically delayed for the time set in the OSTS register.
Page 146 RL78/G1D CHAPTER 6 CLOCK GENERATOR Figure 6-6. Format of Oscillation Stabilization Time Select Register (OSTS) Address: FFFA3H After reset: 07H Symbol OSTS OSTS2 OSTS1 OSTS0 OSTS2 OSTS1 OSTS0 Oscillation stabilization time selection = 10 MHz = 20 MHz 25.6 µs 12.8 µs 51.2 µs 25.6 µs...
Page 147: Peripheral Enable Register 0 (Per0)
RL78/G1D CHAPTER 6 CLOCK GENERATOR 6.3.6 Peripheral enable register 0 (PER0) These registers are used to enable or disable supplying the clock to the peripheral hardware. Clock supply to the hardware that is not used is also stopped so as to decrease the power consumption and noise. To use the peripheral functions below, which are controlled by this register, set (1) the bit corresponding to each function before specifying the initial settings of the peripheral functions.
Page 148 RL78/G1D CHAPTER 6 CLOCK GENERATOR Figure 6-7. Format of Peripheral Enable Register 0 (PER0) (2/2) Address: F00F0H After reset: 00H Symbol <7> <5> <4> <3> <2> <0> PER0 RTCEN ADCEN IICA0EN SAU1EN SAU0EN TAU0EN IICA0EN Control of serial interface IICA0 input clock supply Stops input clock supply.
Page 149: Subsystem Clock Supply Mode Control Register (Osmc)
RL78/G1D CHAPTER 6 CLOCK GENERATOR 6.3.7 Subsystem clock supply mode control register (OSMC) This register is used to reduce power consumption by stopping unnecessary clock functions. If the RTCLPC bit is set to 1, power consumption can be reduced, because clock supply to the peripheral functions, except the real-time clock and 12-bit interval timer, is stopped in STOP mode or HALT mode while subsystem clock is selected as CPU clock.
Page 150: High-Speed On-Chip Oscillator Frequency Select Register (Hocodiv)
RL78/G1D CHAPTER 6 CLOCK GENERATOR 6.3.8 High-speed on-chip oscillator frequency select register (HOCODIV) The frequency of the high-speed on-chip oscillator which is set by an option byte (000C2H) can be changed by using high-speed on-chip oscillator frequency select register (HOCODIV). However, the selectable frequency depends on the FRQSEL3 bit of the option byte (000C2H).
Page 151: High-Speed On-Chip Oscillator Trimming Register (Hiotrm)
RL78/G1D CHAPTER 6 CLOCK GENERATOR 6.3.9 High-speed on-chip oscillator trimming register (HIOTRM) This register is used to adjust the accuracy of the high-speed on-chip oscillator. With self-measurement of the high-speed on-chip oscillator frequency via a timer using high-accuracy external clock input (timer array unit), and so on, the accuracy can be adjusted.
Page 152: System Clock Oscillator
RL78/G1D CHAPTER 6 CLOCK GENERATOR 6.4 System Clock Oscillator 6.4.1 X1 oscillator The X1 oscillator oscillates with a crystal resonator or ceramic resonator (1 to 20 MHz) connected to the X1 and X2 pins. An external clock can also be input. In this case, input the clock signal to the EXCLK pin. To use the X1 oscillator, set bits 7 and 6 (EXCLK, OSCSEL) of the clock operation mode control register (CMC) as follows.
Page 153 RL78/G1D CHAPTER 6 CLOCK GENERATOR Figure 6-12. Example of External Circuit of XT1 Oscillator (a) Crystal oscillation (b) External clock 32.768 External clock EXCLKS Caution When using the X1 oscillator and XT1 oscillator, wire as follows in the area enclosed by the broken lines in the Figures 6-11 and 6-12 to avoid an adverse effect from wiring capacitance.
Page 154 RL78/G1D CHAPTER 6 CLOCK GENERATOR Figure 6-13 shows examples of incorrect resonator connection. Figure 6-13. Examples of Incorrect Resonator Connection (1/2) (a) Too long wiring (b) Crossed signal line PORT (c) The X1 and X2 signal line wires cross. (d) A power supply/GND pattern exists under the X1 and X2 wires.
Page 155 RL78/G1D CHAPTER 6 CLOCK GENERATOR Figure 6-13. Examples of Incorrect Resonator Connection (2/2) (e) Wiring near high alternating current (f) Current flowing through ground line of oscillator (potential at points A, B, and C fluctuates) High current (g) Signals are fetched Caution When X2 and XT1 are wired in parallel, the crosstalk noise of X2 may increase with XT1, resulting in malfunctioning.
Page 156: High-Speed On-Chip Oscillator
RL78/G1D CHAPTER 6 CLOCK GENERATOR 6.4.3 High-speed on-chip oscillator The high-speed on-chip oscillator is incorporated in the RL78/G1D. The frequency can be selected from among 32, 24, 16, 12, 8, 6, 4, 3, 2, or 1 MHz by using the option byte (000C2H). Oscillation can be controlled by bit 0 (HIOSTOP) of the clock operation status control register (CSC).
Page 157: Clock Generator Operation
RL78/G1D CHAPTER 6 CLOCK GENERATOR 6.5 Clock Generator Operation The clock generator generates the following clocks and controls the operation modes of the CPU, such as standby mode (see Figure 6-1). ● Main system clock f MAIN ● High-speed system clock f X1 clock f External main system clock f ●...
Page 158 RL78/G1D CHAPTER 6 CLOCK GENERATOR Figure 6-15. Clock Generator Operation When Power Supply Voltage Is Turned On Lower limit of the operating voltage range VPOR Power-on reset signal At least 10µs <1> RESET pin Switched by software Reset <3> processing time Note3 <...
Page 159: Controlling Clock
RL78/G1D CHAPTER 6 CLOCK GENERATOR 6.6 Controlling Clock 6.6.1 Example of setting high-speed on-chip oscillator After a reset release, the CPU/peripheral hardware clock (f ) always starts operating with the high-speed on-chip oscillator clock. The frequency of the high-speed on-chip oscillator can be selected from 32, 24, 16, 12, 8, 6, 4, 3, 2, and 1 MHz by using FRQSEL0 to FRQSEL3 of the option byte (000C2H).
Page 160: Example Of Setting X1 Oscillation Clock
RL78/G1D CHAPTER 6 CLOCK GENERATOR 6.6.2 Example of setting X1 oscillation clock After a reset release, the CPU/peripheral hardware clock (f ) always starts operating with the high-speed on-chip oscillator clock. To subsequently change the clock to the X1 oscillation clock, set the oscillator and start oscillation by using the oscillation stabilization time select register (OSTS) and clock operation mode control register (CMC) and clock operation status control register (CSC) and wait for oscillation to stabilize by using the oscillation stabilization time counter status register (OSTC).
Page 161: Example Of Setting Xt1 Oscillation Clock
RL78/G1D CHAPTER 6 CLOCK GENERATOR 6.6.3 Example of setting XT1 oscillation clock After a reset release, the CPU/peripheral hardware clock (f ) always starts operating with the high-speed on-chip oscillator clock. To subsequently change the clock to the XT1 oscillation clock, set the oscillator and start oscillation by using the subsystem clock supply mode control register (OSMC), clock operation mode control register (CMC), and clock operation status control register (CSC), set the XT1 oscillation clock to f by using the system clock control register...
Page 162: Cpu Clock Status Transition Diagram
RL78/G1D CHAPTER 6 CLOCK GENERATOR 6.6.4 CPU clock status transition diagram Figure 6-16 shows the CPU clock status transition diagram of this product. Figure 6-16. CPU Clock Status Transition Diagram High-speed on-chip oscillator: Woken up Power ON X1 oscillation/EXCLK input: Stops (input port mode) XT1 oscillation/EXCLKS input: Stops (input port mode) Lower limit of the operating voltage range Reset release...
Page 163 RL78/G1D CHAPTER 6 CLOCK GENERATOR Table 6-3 shows transition of the CPU clock and examples of setting the SFR registers. Table 6-3. CPU Clock Transition and SFR Register Setting Examples (1/5) (1) CPU operating with high-speed on-chip oscillator clock (B) after reset release (A) Status Transition SFR Register Setting (A) →...
Page 164 RL78/G1D CHAPTER 6 CLOCK GENERATOR Table 6-3. CPU Clock Transition and SFR Register Setting Examples (2/5) (4) CPU clock changing from high-speed on-chip oscillator clock (B) to high-speed system clock (C) (Setting sequence of SFR registers) Note 1 Setting Flag of SFR Register CMC Register OSTS OSTC Register...
Page 165 RL78/G1D CHAPTER 6 CLOCK GENERATOR Table 6-3. CPU Clock Transition and SFR Register Setting Examples (3/5) (6) CPU clock changing from high-speed system clock (C) to high-speed on-chip oscillator clock (B) (Setting sequence of SFR registers) Setting Flag of SFR Register CSC Register Oscillation accuracy CKC Register...
Page 166 RL78/G1D CHAPTER 6 CLOCK GENERATOR Table 6-3. CPU Clock Transition and SFR Register Setting Examples (4/5) (9) CPU clock changing from subsystem clock (D) to high-speed system clock (C) (Setting sequence of SFR registers) Setting Flag of SFR Register OSTS CSC Register OSTC Register CKC Register...
Page 167 RL78/G1D CHAPTER 6 CLOCK GENERATOR Table 6-3. CPU Clock Transition and SFR Register Setting Examples (5/5) (11) ● STOP mode (H) set while CPU is operating with high-speed on-chip oscillator clock (B) ● STOP mode (I) set while CPU is operating with high-speed system clock (C) (Setting sequence) Status Transition Setting...
Page 168: Condition Before Changing Cpu Clock And Processing After Changing Cpu Clock
RL78/G1D CHAPTER 6 CLOCK GENERATOR 6.6.5 Condition before changing CPU clock and processing after changing CPU clock Condition before changing the CPU clock and processing after changing the CPU clock are shown below. Table 6-4. Changing CPU Clock (1/2) CPU Clock Condition Before Change Processing After Change Before Change...
Page 169 RL78/G1D CHAPTER 6 CLOCK GENERATOR Table 6-4. Changing CPU Clock (2/2) CPU Clock Condition Before Change Processing After Change Before Change After Change XT1 clock High-speed on- Oscillation of high-speed on-chip oscillator After confirmation of switching CPU clock to chip oscillator and selection of high-speed on-chip status before change, XT1 oscillation can clock...
Page 170: Time Required For Switchover Of Cpu Clock And System Clock
RL78/G1D CHAPTER 6 CLOCK GENERATOR 6.6.6 Time required for switchover of CPU clock and system clock By setting bits 4 and 6 (MCM0, CSS) of the system clock control register (CKC), the CPU clock can be switched (between the main system clock and the subsystem clock), and main system clock can be switched (between the high- speed on-chip oscillator clock and the high-speed system clock).
Page 171: Conditions Before Clock Oscillation Is Stopped
RL78/G1D CHAPTER 6 CLOCK GENERATOR 6.6.7 Conditions before clock oscillation is stopped The following lists the register flag settings for stopping the clock oscillation (disabling external clock input) and conditions before the clock oscillation is stopped. The condition before stopping clock must be confirmed before the stopping. Table 6-8.
Page 172: Resonator And Oscillator Constants
RL78/G1D CHAPTER 6 CLOCK GENERATOR 6.7 Resonator and Oscillator Constants The resonators for which the operation is verified and their oscillator constants are shown below. Cautions 1. The constants for these oscillator circuits are reference values based on specific environments set up for evaluation by the manufacturers.
Page 173 RL78/G1D CHAPTER 6 CLOCK GENERATOR (1) X1 oscillation: As of April, 2015 (1/2) Note 3 Manufacturer Resonator Part Number SMD/ Frequency Flash Recommended Circuit Oscillation Voltage Note 2 Lead (MHz) operation Constants (reference) Range (V) Note 1 mode C1 (pF) C2 (pF) Rd (kΩ) MIN.
Page 174 RL78/G1D CHAPTER 6 CLOCK GENERATOR As of April, 2015 (2/2) Note 2 Manufacturer Resonator Part Number SMD/ Frequency Flash Recommended Circuit Oscillation Voltage Lead (MHz) operation Constants (reference) Range (V) Note 1 mode C1 (pF) C2 (pF) Rd (kΩ) MIN. MAX.
Page 175 RL78/G1D CHAPTER 6 CLOCK GENERATOR (2) XT1 oscillation: Crystal resonator As of April, 2015 Note Manufacturer Part Number SMD/ Frequency Load XT1 oscillation Recommended Circuit Oscillation Voltage Note 1 Lead (kHz) Capacitance mode Constants Range CL (pF) C3 (pF) C4 (pF) Rd (kΩ) MIN. (V) MAX. (V) Note 3 Seiko SSP-T7-F...
Page 176 RL78/G1D CHAPTER 6 CLOCK GENERATOR (3) RF reference clock oscillation: Crystal resonator Manufacturer Part Number SMD/Lead Frequency Load Recommended Oscillation (MHz) Capacitance Circuit Constants Voltage CL (pF) (reference) Range (V) C5(pF) C6(pF) MIN. MAX. Nihon Dempa NX1612SA-32.000M 32.00 Note Kogyo Co., Ltd. HZ-CHP-CIS-3 Note When using this resonator, for details about the matching, contact Nihon Dempa Kogyo Co., Ltd (http://www.ndk.com/en).
Page 177: Chapter 7 Timer Array Unit
RL78/G1D CHAPTER 7 TIMER ARRAY UNIT CHAPTER 7 TIMER ARRAY UNIT The timer array unit has eight 16-bit timers. Each 16-bit timer is called a channel and can be used as an independent timer. In addition, two or more “channels” can be used to create a high-accuracy timer.
Page 178: Functions Of Timer Array Unit
RL78/G1D CHAPTER 7 TIMER ARRAY UNIT 7.1 Functions of Timer Array Unit Timer array unit has the following functions. 7.1.1 Independent channel operation function By operating a channel independently, it can be used for the following purposes without being affected by the operation mode of other channels.
Page 179: Simultaneous Channel Operation Function
RL78/G1D CHAPTER 7 TIMER ARRAY UNIT (6) Measurement of high-/low-level width of input signal Counting is started by a single edge of the signal input to the timer input pin (TImn), and the count value is captured at the other edge. In this way, the high-level or low-level width of the input signal can be measured. Capture operation Timer input (TImn)
Page 180: 8-Bit Timer Operation Function (Channel 1 And 3 Only)
RL78/G1D CHAPTER 7 TIMER ARRAY UNIT (3) Multiple PWM (Pulse Width Modulation) output By extending the PWM function and using one master channel and two or more slave channels, up to seven types of PWM signals that have a specific period and a specified duty factor can be generated. Compare operation Interrupt signal (INTTMmn) Operation clock...
Page 181: Configuration Of Timer Array Unit
RL78/G1D CHAPTER 7 TIMER ARRAY UNIT 7.2 Configuration of Timer Array Unit Timer array unit includes the following hardware. Table 7-1. Configuration of Timer Array Unit Item Configuration Timer/counter Timer count register mn (TCRmn) Register Timer data register mn (TDRmn) Timer input TI00 to TI07 pins Timer output...
Page 182 RL78/G1D CHAPTER 7 TIMER ARRAY UNIT Table 7-2. Timer I/O Pins provided in Each Product Timer array unit channels I/O Pins of Each Product Channel 0 P00/TI00, P01/TO00 P16/TI01/TO01 Channel 1 Channel 2 P15/(TI02/TO02) P14/(TI03/TO03) Channel 3 Unit 0 Channel 4 P13/(TI04/TO04) P12/(TI05/TO05) Channel 5...
Page 183 RL78/G1D CHAPTER 7 TIMER ARRAY UNIT Figure 7-1. Entire Configuration of Timer Array Unit 0 Timer clock select register 0 (TPS0) PRS031 PRS030 PRS021 PRS020 PRS013 PRS012 PRS011 PRS010 PRS003 PRS002 PRS001 PRS000 Prescaler to f Peripheral enable Selector Selector register 0 TAU0EN (PER0)
Page 184 RL78/G1D CHAPTER 7 TIMER ARRAY UNIT Figure 7-2. Internal Block Diagram of Channels 0, 2, 4, 6 of Timer Array Unit 0 Note 1 Input signal from the master channel CK00 Timer controller Output TCLK TO0n controller CK01 Output latch Mode (Pxx) PMxx...
Page 185 RL78/G1D CHAPTER 7 TIMER ARRAY UNIT Figure 7-4. Internal Block Diagram of Channel 5 of Timer Array Unit 0 Input signal from the master channel CK00 Timer controller Output TCLK TO05 controller CK01 Output latch Mode PMxx (Pxx) selection Interrupt INTTM05 Timer input select controller...
Page 186: Timer Count Register Mn (Tcrmn)
RL78/G1D CHAPTER 7 TIMER ARRAY UNIT 7.2.1 Timer count register mn (TCRmn) The TCRmn register is a 16-bit read-only register and is used to count clocks. The value of this counter is incremented or decremented in synchronization with the rising edge of a count clock. Whether the counter is incremented or decremented depends on the operation mode that is selected by the MDmn3 to MDmn0 bits of timer mode register mn (TMRmn) (refer to 7.3.3 Timer mode register mn (TMRmn)).
Page 187 RL78/G1D CHAPTER 7 TIMER ARRAY UNIT The count value can be read by reading timer count register mn (TCRmn). The count value is set to FFFFH in the following cases. ● When the reset signal is generated ● When the TAUmEN bit of peripheral enable register 0 (PER0) is cleared ●...
Page 188: Timer Data Register Mn (Tdrmn)
RL78/G1D CHAPTER 7 TIMER ARRAY UNIT 7.2.2 Timer data register mn (TDRmn) This is a 16-bit register from which a capture function and a compare function can be selected. The capture or compare function can be switched by selecting an operation mode by using the MDmn3 to MDmn0 bits of timer mode register mn (TMRmn).
Page 189: Registers Controlling Timer Array Unit
RL78/G1D CHAPTER 7 TIMER ARRAY UNIT 7.3 Registers Controlling Timer Array Unit Timer array unit is controlled by the following registers. ●Peripheral enable register 0 (PER0) ●Timer clock select register m (TPSm) ●Timer mode register mn (TMRmn) ●Timer status register mn (TSRmn) ●Timer channel enable status register m (TEm) ●Timer channel start register m (TSm) ●Timer channel stop register m (TTm)
Page 190: Peripheral Enable Register 0 (Per0)
RL78/G1D CHAPTER 7 TIMER ARRAY UNIT 7.3.1 Peripheral enable register 0 (PER0) This registers is used to enable or disable supplying the clock to the peripheral hardware. Clock supply to a hardware macro that is not used is stopped in order to reduce the power consumption and noise. When the timer array unit 0 is used, be sure to set bit 0 (TAU0EN) of this register to 1.
Page 191: Timer Clock Select Register M (Tpsm)
RL78/G1D CHAPTER 7 TIMER ARRAY UNIT 7.3.2 Timer clock select register m (TPSm) The TPSm register is a 16-bit register that is used to select two types or four types of operation clocks (CKm0, CKm1, CKm2, CKm3) that are commonly supplied to each channel. CKm0 is selected by using bits 3 to 0 of the TPSm register, and CKm1 is selected by using bits 7 to 4 of the TPSm register.
Page 192 RL78/G1D CHAPTER 7 TIMER ARRAY UNIT Figure 7-10. Format of Timer Clock Select register m (TPSm) (1/2) Address: F01B6H, F01B7H (TPS0) After reset: 0000H Symbol TPSm Note Selection of operation clock (CKmk) (k = 0, 1) = 2 MHz = 5 MHz f = 10 MHz f = 20 MHz f = 32 MHz...
Page 193 RL78/G1D CHAPTER 7 TIMER ARRAY UNIT Figure 7-10. Format of Timer Clock Select register m (TPSm) (2/2) Address: F01B6H, F01B7H (TPS0) After reset: 0000H Symbol TPSm Note Selection of operation clock (CKm2) = 2 MHz = 5 MHz f = 10 MHz f = 20 MHz f = 32 MHz 1 MHz...
Page 194: Timer Mode Register Mn (Tmrmn)
RL78/G1D CHAPTER 7 TIMER ARRAY UNIT 7.3.3 Timer mode register mn (TMRmn) The TMRmn register sets an operation mode of channel n. This register is used to select the operation clock (f select the count clock, select the master/slave, select the 16 or 8-bit timer (only for channel 1), specify the start trigger and capture trigger, select the valid edge of the timer input, and specify the operation mode (interval, capture, event counter, one-count, or capture and one-count).
Page 195 RL78/G1D CHAPTER 7 TIMER ARRAY UNIT Figure 7-11. Format of Timer Mode Register mn (TMRmn) (1/4) Address: F0190H, F0191H (TMR00) to F019EH, F019FH (TMR07) After reset: 0000H Symbol TMRmn MAST ERmn (mn = 02, 04, Symbol TMRmn SPLIT (mn = 01, 03) Symbol Note TMRmn...
Page 196 RL78/G1D CHAPTER 7 TIMER ARRAY UNIT Figure 7-11. Format of Timer Mode Register mn (TMRmn) (2/4) Address: F0190H, F0191H (TMR00) to F019EH, F019FH (TMR07) After reset: 0000H Symbol TMRmn MAST ERmn (mn = 02, 04, 06) Symbol TMRmn SPLIT (mn = 01, Symbol Note TMRmn...
Page 197 RL78/G1D CHAPTER 7 TIMER ARRAY UNIT Figure 7-11. Format of Timer Mode Register mn (TMRmn) (3/4) Address: F0190H, F0191H (TMR00) to F019EH, F019FH (TMR07) After reset: 0000H Symbol TMRmn MAST ERmn (mn = 02, 04, 06) Symbol TMRmn SPLIT (mn = 01, Symbol Note TMRmn...
Page 198 RL78/G1D CHAPTER 7 TIMER ARRAY UNIT Figure 7-11. Format of Timer Mode Register mn (TMRmn) (4/4) Address: F0190H, F0191H (TMR00) to F019EH, F019FH (TMR07) After reset: 0000H Symbol TMRmn MAST ERmn (mn = 02, 04, 06) Symbol TMRmn SPLIT (mn = 01, Symbol Note TMRmn...
Page 199 RL78/G1D CHAPTER 7 TIMER ARRAY UNIT Notes 1. Bit 11 is a read-only bit and fixed to 0. Writing to this bit is ignored. 2. In one-count mode, interrupt output (INTTMmn) when starting a count operation and TOmn output are not controlled.
Page 200: Timer Status Register Mn (Tsrmn)
RL78/G1D CHAPTER 7 TIMER ARRAY UNIT 7.3.4 Timer status register mn (TSRmn) The TSRmn register indicates the overflow status of the counter of channel n. The TSRmn register is valid only in the capture mode (MDmn3 to MDmn1 = 010B) and capture & one-count mode (MDmn3 to MDmn1 = 110B).
Page 201: Timer Channel Enable Status Register M (Tem)
RL78/G1D CHAPTER 7 TIMER ARRAY UNIT 7.3.5 Timer channel enable status register m (TEm) The TEm register is used to enable or stop the timer operation of each channel. Each bit of the TEm register corresponds to each bit of the timer channel start register m (TSm) and the timer channel stop register m (TTm).
Page 202: Timer Channel Start Register M (Tsm)
RL78/G1D CHAPTER 7 TIMER ARRAY UNIT 7.3.6 Timer channel start register m (TSm) The TSm register is a trigger register that is used to initialize timer count register mn (TCRmn) and start the counting operation of each channel. When a bit of this register is set to 1, the corresponding bit of timer channel enable status register m (TEm) is set to 1. The TSmn, TSHm1, TSHm3 bits are immediately cleared when operation is enabled (TEmn, TEHm1, TEHm3 = 1), because they are trigger bits.
Page 203: Timer Channel Stop Register M (Ttm)
RL78/G1D CHAPTER 7 TIMER ARRAY UNIT 7.3.7 Timer channel stop register m (TTm) The TTm register is a trigger register that is used to stop the counting operation of each channel. When a bit of this register is set to 1, the corresponding bit of timer channel enable status register m (TEm) is cleared to 0.
Page 204: Timer Input Select Register 0 (Tis0)
RL78/G1D CHAPTER 7 TIMER ARRAY UNIT 7.3.8 Timer input select register 0 (TIS0) The TIS0 register is used to select the channel 5 of unit 0 timer input.. The TIS0 register can be set by an 8-bit memory manipulation instruction. Reset signal generation clears this register to 00H.
Page 205: Timer Output Enable Register 0 (Toe0)
RL78/G1D CHAPTER 7 TIMER ARRAY UNIT 7.3.9 Timer output enable register 0 (TOE0) The TOE0 register is used to enable or disable timer output of each channel. Channel n for which timer output has been enabled becomes unable to rewrite the value of the TO0n bit of timer output register 0 (TO0) described later by software, and the value reflecting the setting of the timer output function through the count operation is output from the timer output pin (TO0n).
Page 206: Timer Output Register 0 (To0)
RL78/G1D CHAPTER 7 TIMER ARRAY UNIT 7.3.10 Timer output register 0 (TO0) The TOm register is a buffer register of timer output of each channel. The value of each bit in this register is output from the timer output pin (TO0n) of each channel. The TO0n bit oh this register can be rewritten by software only when timer output is disabled (TOE0n = 0).
Page 207: Timer Output Level Register 0 (Tol0)
RL78/G1D CHAPTER 7 TIMER ARRAY UNIT 7.3.11 Timer output level register 0 (TOL0) The TOL0 register is a register that controls the timer output level of each channel. The setting of the inverted output of channel n by this register is reflected at the timing of set or reset of the timer output signal while the timer output is enabled (TOE0n = 1) in the Slave channel output mode (TOM0n = 1).
Page 208: Timer Output Mode Register 0 (Tom0)
RL78/G1D CHAPTER 7 TIMER ARRAY UNIT 7.3.12 Timer output mode register 0 (TOM0) The TOM0 register is used to control the timer output mode of each channel. When a channel is used for the independent channel operation function, set the corresponding bit of the channel to be used to 0.
Page 209: Noise Filter Enable Register 1 (Nfen1)
RL78/G1D CHAPTER 7 TIMER ARRAY UNIT 7.3.13 Noise filter enable register 1 (NFEN1) The NFEN1 register is used to set whether the noise filter can be used for the timer input signal to each channel. Enable the noise filter by setting the corresponding bits to 1 on the pins in need of noise removal. When the noise filter is enabled, after synchronization with the operating clock (f ) for the target channel, whether the signal keeps the same value for two clock cycles is detected.
Page 210: Registers Controlling Port Functions Of Pins To Be Used For Timer I/O
RL78/G1D CHAPTER 7 TIMER ARRAY UNIT 7.3.14 Registers controlling port functions of pins to be used for timer I/O Using port pins for the timer array unit functions requires setting of the registers that control the port functions multiplexed on the target pins (port mode register (PMxx), port register (Pxx), and port mode control register (PMCxx)). For details, see 5.3.1 Port mode registers (PMxx), 5.3.2 Port registers (Pxx), and 5.3.6 Port mode control registers (PMCxx).
Page 211: Basic Rules Of Timer Array Unit
RL78/G1D CHAPTER 7 TIMER ARRAY UNIT 7.4 Basic Rules of Timer Array Unit 7.4.1 Basic rules of simultaneous channel operation function When simultaneously using multiple channels, namely, a combination of a master channel (a reference timer mainly counting the cycle) and slave channels (timers operating according to the master channel), the following rules apply. (1) Only an even channel (channel 0, 2, 4, etc.) can be set as a master channel.
Page 212 RL78/G1D CHAPTER 7 TIMER ARRAY UNIT Example TAU0 Channel group 1 CK00 Channel 0: Master (Simultaneous channel operation function) Channel 1: Slave Channel group 2 Channel 2: Slave (Simultaneous channel operation function) Channel 3: independent channel operation function * The operating clock of channel group 1 may CK01 be different from that of channel group 2.
Page 213: Basic Rules Of 8-Bit Timer Operation Function (Channels 1 And 3 Only)
RL78/G1D CHAPTER 7 TIMER ARRAY UNIT 7.4.2 Basic rules of 8-bit timer operation function (channels 1 and 3 only) The 8-bit timer operation function makes it possible to use a 16-bit timer channel in a configuration consisting of two 8- bit timer channels.
Page 214: Operation Of Counter
RL78/G1D CHAPTER 7 TIMER ARRAY UNIT 7.5 Operation of Counter 7.5.1 Count clock (f TCLK The count clock (f ) of the timer array unit can be specified as follows by CCSmn bit of timer mode register mn TCLK (TMRmn). ●...
Page 215 RL78/G1D CHAPTER 7 TIMER ARRAY UNIT (2) When valid edge of input signal via the TImn pin is selected (CCSmn = 1) The count clock (f ) becomes the signal that detects valid edge of input signal via the TImn pin and synchronizes TCLK next rising f .
Page 216: Start Timing Of Counter
RL78/G1D CHAPTER 7 TIMER ARRAY UNIT 7.5.2 Start timing of counter Timer count register mn (TCRmn) becomes enabled to operation by setting of TSmn bit of timer channel start register m (TSm). Operations from count operation enabled state to timer count Register mn (TCRmn) count start is shown in Table 7-6. Table 7-6.
Page 217: Operation Of Counter
RL78/G1D CHAPTER 7 TIMER ARRAY UNIT 7.5.3 Operation of counter Here, the counter operation in each mode is explained. (1) Operation of interval timer mode <1> Operation is enabled (TEmn = 1) by writing 1 to the TSmn bit. Timer count register mn (TCRmn) holds the initial value until count clock generation.
Page 218 RL78/G1D CHAPTER 7 TIMER ARRAY UNIT (2) Operation of event counter mode <1> Timer count register mn (TCRmn) holds its initial value while operation is stopped (TEmn = 0). <2> Operation is enabled (TEmn = 1) by writing 1 to the TSmn bit. <3>...
Page 219 RL78/G1D CHAPTER 7 TIMER ARRAY UNIT (3) Operation of capture mode (input pulse interval measurement) <1> Operation is enabled (TEmn = 1) by writing 1 to the TSmn bit. <2> Timer count register mn (TCRmn) holds the initial value until count clock generation. <3>...
Page 220 RL78/G1D CHAPTER 7 TIMER ARRAY UNIT (4) Operation of one-count mode <1> Operation is enabled (TEmn = 1) by writing 1 to the TSmn bit. <2> Timer count register mn (TCRmn) holds the initial value until start trigger generation. <3> Rising edge of the TImn input is detected. <4>...
Page 221 RL78/G1D CHAPTER 7 TIMER ARRAY UNIT (5) Operation of capture & one-count mode (high-level width measurement) <1> Operation is enabled (TEmn = 1) by writing 1 to the TSmn bit of timer channel start register m (TSm). <2> Timer count register mn (TCRmn) holds the initial value until start trigger generation. <3>...
Page 222: Channel Output (To0N Pin) Control
RL78/G1D CHAPTER 7 TIMER ARRAY UNIT 7.6 Channel Output (TO0n pin) Control 7.6.1 TO0n pin output circuit configuration Figure 7-29. Output Circuit Configuration <5> TO0n register Interrupt signal of the master channel (INTTMmn) TO0n pin Interrupt signal of the slave channel (INTTMmp) Reset/toggle <1>...
Page 223: To0N Pin Output Setting
RL78/G1D CHAPTER 7 TIMER ARRAY UNIT 7.6.2 TO0n pin output setting The following figure shows the procedure and status transition of the TO0n output pin from initial setting to timer operation start. Figure 7-30. Status Transition from Timer Output Setting to Operation Start TCRmn Undefined value (FFFFH after reset) (Counter)
Page 224: Cautions On Channel Output Operation
RL78/G1D CHAPTER 7 TIMER ARRAY UNIT 7.6.3 Cautions on channel output operation (1) Changing values set in the registers TO0, TOE0, and TOL0 during timer operation Since the timer operations (operations of timer count register mn (TCRmn) and timer data register mn (TDRmn)) are independent of the TO0n output circuit and changing the values set in timer output register 0 (TO0), timer output enable register 0 (TOE0), and timer output level register 0 (TOL0) does not affect the timer operation, the values can be changed during timer operation.
Page 225 RL78/G1D CHAPTER 7 TIMER ARRAY UNIT (2) Default level of TO0n pin and output level after timer operation start The change in the output level of the TO0n pin when timer output register 0 (TO0) is written while timer output is disabled (TOE0n = 0), the initial level is changed, and then timer output is enabled (TOE0n = 1) before port output is enabled, is shown below.
Page 226 RL78/G1D CHAPTER 7 TIMER ARRAY UNIT (b) When operation starts with slave channel output mode (TOM0p = 1) setting (PWM output)) When slave channel output mode (TOM0p = 1), the active level is determined by timer output level register 0 (TOL0) setting.
Page 227 RL78/G1D CHAPTER 7 TIMER ARRAY UNIT (3) Operation of TO0n pin in slave channel output mode (TOM0n = 1) (a) When timer output level register 0 (TOL0) setting has been changed during timer operation When the TOL0 register setting has been changed during timer operation, the setting becomes valid at the generation timing of the TO0n pin change condition.
Page 228 RL78/G1D CHAPTER 7 TIMER ARRAY UNIT Figure 7-34. Set/Reset Timing Operating Statuses (1) Basic operation timing TCLK INTTMmn Internal reset Master signal channel TOmn pin/ TOmn Toggle Toggle Internal set signal 1 clock delay INTTMmp Slave channel Internal reset signal TOmp pin/ TOmp Reset...
Page 229: Collective Manipulation Of To0N Bit
RL78/G1D CHAPTER 7 TIMER ARRAY UNIT 7.6.4 Collective manipulation of TO0n bit In timer output register 0 (TO0), the setting bits for all the channels are located in one register in the same way as timer channel start register m (TSm). Therefore, the TO0n bit of all the channels can be manipulated collectively. Only the desired bits can also be manipulated by enabling writing only to the TO0n bits (TOE0n = 0) that correspond to the relevant bits of the channel used to perform output (TO0n).
Page 230: Timer Interrupt And To0N Pin Output At Operation Start
RL78/G1D CHAPTER 7 TIMER ARRAY UNIT 7.6.5 Timer interrupt and TO0n pin output at operation start In the interval timer mode or capture mode, the MDmn0 bit in timer mode register mn (TMRmn) sets whether or not to generate a timer interrupt at count start. When MDmn0 is set to 1, the count operation start timing can be known by the timer interrupt (INTTMmn) generation.
Page 231: Timer Input (Ti0N) Control
RL78/G1D CHAPTER 7 TIMER ARRAY UNIT 7.7 Timer Input (TI0n) Control 7.7.1 TI0n input circuit configuration A signal is input from a timer input pin, goes through a noise filter and an edge detector, and is sent to a timer controller. Enable the noise filter for the pin in need of noise removal.
Page 232: Cautions On Channel Input Operation
RL78/G1D CHAPTER 7 TIMER ARRAY UNIT 7.7.3 Cautions on channel input operation When a timer input pin is set as unused, the operating clock is not supplied to the noise filter. Therefore, after settings are made to use the timer input pin, the following wait time is necessary before a trigger is specified to enable operation of the channel corresponding to the timer input pin.
Page 233: Independent Channel Operation Function Of Timer Array Unit
RL78/G1D CHAPTER 7 TIMER ARRAY UNIT 7.8 Independent Channel Operation Function of Timer Array Unit 7.8.1 Operation as interval timer/square wave output (1) Interval timer The timer array unit can be used as a reference timer that generates INTTMmn (timer interrupt) at fixed intervals. The interrupt generation period can be calculated by the following expression.
Page 234 RL78/G1D CHAPTER 7 TIMER ARRAY UNIT Figure 7-40. Block Diagram of Operation as Interval Timer/Square Wave Output CKm1 Note Operation clock Timer counter Output CKm0 TO0n pin register mn (TCRmn) controller Interrupt Timer data Interrupt signal TSmn controller register mn(TDRmn) (INTTMmn) Note When channels 1 and 3, the clock can be selected from CKm0, CKm1, CKm2 and CKm3.
Page 235 RL78/G1D CHAPTER 7 TIMER ARRAY UNIT Figure 7-42. Example of Set Contents of Registers During Operation as Interval Timer/Square Wave Output (1/2) (a) Timer mode register mn (TMRmn) TMRmn Note CKSmn1 CKSmn0 CCSmn STSmn2 STSmn1 STSmn0 CISmn1 CISmn0 MDmn3 MDmn2 MDmn1 MDmn0 Operation mode of channel n...
Page 236 RL78/G1D CHAPTER 7 TIMER ARRAY UNIT Figure 7-42. Example of Set Contents of Registers During Operation as Interval Timer/Square Wave Output (2/2) (d) Timer output level register 0 (TOL0) Bit n TOL0 0: Cleared to 0 when TOM0n = 0 (master channel output mode) TOL0n (e) Timer output mode register 0 (TOM0) Bit n...
Page 237 RL78/G1D CHAPTER 7 TIMER ARRAY UNIT Figure 7-43. Operation Procedure of Interval Timer/Square Wave Output Function (1/2) Software Operation Hardware Status Power-off status default (Clock supply is stopped and writing to each register is setting disabled.) Sets the TAUmEN bit of peripheral enable register 0 Power-on status.
Page 238 RL78/G1D CHAPTER 7 TIMER ARRAY UNIT Figure 7-43. Operation Procedure of Interval Timer/Square Wave Output Function (2/2) Software Operation Hardware Status To hold the TO0n pin output level Clears the TO0n bit to 0 after the value to stop be held is set to the port register. The TO0n pin output level is held by port function.
Page 239: Operation As External Event Counter
RL78/G1D CHAPTER 7 TIMER ARRAY UNIT 7.8.2 Operation as external event counter The timer array unit can be used as an external event counter that counts the number of times the valid input edge (external event) is detected in the TImn pin. When a specified count value is reached, the event counter generates an interrupt.
Page 240 RL78/G1D CHAPTER 7 TIMER ARRAY UNIT Figure 7-45. Example of Basic Timing of Operation as External Event Counter TSmn TEmn TImn TCRmn 0000H TDRmn 0003H 0002H INTTMmn 4 events 4 events 3 events Remarks 1. m: Unit number (m = 0), n: Channel number (n = 0 to 7) 2.
Page 241 RL78/G1D CHAPTER 7 TIMER ARRAY UNIT Figure 7-46. Example of Set Contents of Registers in External Event Counter Mode (1/2) (a) Timer mode register mn (TMRmn) TMRmn Note CKSmn1 CKSmn0 CCSmn STSmn2 STSmn1 STSmn0 CISmn1 CISmn0 MDmn3 MDmn2 MDmn1 MDmn0 Operation mode of channel n 011B: Event count mode Setting of operation when counting is started...
Page 242 RL78/G1D CHAPTER 7 TIMER ARRAY UNIT Figure 7-46. Example of Set Contents of Registers in External Event Counter Mode (2/2) (d) Timer output level register 0 (TOL0) Bit n TOL0 0: Cleared to 0 when TOM0n = 0 (master channel output mode). TOL0n (e) Timer output mode register 0 (TOM0) Bit n...
Page 243 RL78/G1D CHAPTER 7 TIMER ARRAY UNIT Figure 7-47. Operation Procedure When External Event Counter Function Is Used Software Operation Hardware Status Power-off status default (Clock supply is stopped and writing to each register is setting disabled.) Sets the TAUmEN bit of peripheral enable register 0 (PER0) to 1.
Page 244: Operation As Frequency Divider (Channel 0 Of Unit 0 Only)
RL78/G1D CHAPTER 7 TIMER ARRAY UNIT 7.8.3 Operation as frequency divider (channel 0 of unit 0 only) The timer array unit can be used as a frequency divider that divides a clock input to the TI00 pin and outputs the result from the TO00 pin.
Page 245 RL78/G1D CHAPTER 7 TIMER ARRAY UNIT Figure 7-49. Example of Basic Timing of Operation as Frequency Divider (MD000 = 1) TS00 TE00 TI00 TCR00 0000H TDR00 0002H 0001H TO00 INTTM00 Divided Divided by 6 by 4 Remark TS00: Bit n of timer channel start register 0 (TS0) TE00: Bit n of timer channel enable status register 0 (TE0) TI00:...
Page 246 RL78/G1D CHAPTER 7 TIMER ARRAY UNIT Figure 7-50. Example of Set Contents of Registers During Operation as Frequency Divider (a) Timer mode register 00 (TMR00) TMR00 CKS0n1 CKS0n0 CCS00 STS002 STS001 STS000 CIS001 CIS000 MD003 MD002 MD001 MD000 Operation mode of channel 0 000B: Interval timer Setting of operation when counting is started 0: Neither generates INTTM00 nor inverts...
Page 247 RL78/G1D CHAPTER 7 TIMER ARRAY UNIT Figure 7-51. Operation Procedure When Frequency Divider Function Is Used Software Operation Hardware Status Power-off status default (Clock supply is stopped and writing to each register is setting disabled.) Sets the TAU0EN bit of peripheral enable register 0 (PER0) to 1.
Page 248: Operation As Input Pulse Interval Measurement
RL78/G1D CHAPTER 7 TIMER ARRAY UNIT 7.8.4 Operation as input pulse interval measurement The count value can be captured at the TImn valid edge and the interval of the pulse input to TImn can be measured. In addition, the count value can be captured by using software operation (TSmn = 1) as a capture trigger while the TEmn bit is set to 1.
Page 249 RL78/G1D CHAPTER 7 TIMER ARRAY UNIT Figure 7-53. Example of Basic Timing of Operation as Input Pulse Interval Measurement (MDmn0 = 0) TSmn TEmn TImn FFFFH TCRmn 0000H TDRmn 0000H INTTMmn Remarks 1. m: Unit number (m = 0)n: Channel number (n = 0 to 7) 2.
Page 250 RL78/G1D CHAPTER 7 TIMER ARRAY UNIT Figure 7-54. Example of Set Contents of Registers to Measure Input Pulse Interval (a) Timer mode register mn (TMRmn) TMRmn Note CKSmn1 CKSmn0 CCSmn STSmn2 STSmn1 STSmn0 CISmn1 CISmn0 MDmn3 MDmn2 MDmn1 MDmn0 Operation mode of channel n 010B: Capture mode Setting of operation when counting is started 0: Does not generate INTTMmn when...
Page 251 RL78/G1D CHAPTER 7 TIMER ARRAY UNIT Figure 7-55. Operation Procedure When Input Pulse Interval Measurement Function Is Used Software Operation Hardware Status Power-off status default (Clock supply is stopped and writing to each register is setting disabled.) Sets the TAUmEN bit of peripheral enable register 0 (PER0) to 1.
Page 252: Operation As Input Signal High-/Low-Level Width Measurement
RL78/G1D CHAPTER 7 TIMER ARRAY UNIT 7.8.5 Operation as input signal high-/low-level width measurement By starting counting at one edge of the TImn pin input and capturing the number of counts at another edge, the signal width (high-level width/low-level width) of TImn can be measured. The signal width of TImn can be calculated by the following expression.
Page 253 RL78/G1D CHAPTER 7 TIMER ARRAY UNIT Figure 7-56. Block Diagram of Operation as Input Signal High-/Low-Level Width Measurement CKm1 Operation clock Note Timer counter CKm0 register mn (TCRmn) TNFENxx Timer data Interrupt Noise Edge Interrupt signal TImn pin register mn (TDRmn) controller filter detection...
Page 254 RL78/G1D CHAPTER 7 TIMER ARRAY UNIT Figure 7-58. Example of Set Contents of Registers to Measure Input Signal High-/Low-Level Width (a) Timer mode register mn (TMRmn) TMRmn Note CKSmn1 CKSmn0 CCSmn STSmn2 STSmn1 STSmn0 CISmn1 CISmn0 MDmn3 MDmn2 MDmn1 MDmn0 Operation mode of channel n 110B: Capture &...
Page 255 RL78/G1D CHAPTER 7 TIMER ARRAY UNIT Figure 7-59. Operation Procedure When Input Signal High-/Low-Level Width Measurement Function Is Used Software Operation Hardware Status Power-off status default (Clock supply is stopped and writing to each register is setting disabled.) Sets the TAUmEN bit of peripheral enable register 0 Power-on status.
Page 256: Operation As Delay Counter
RL78/G1D CHAPTER 7 TIMER ARRAY UNIT 7.8.6 Operation as delay counter It is possible to start counting down when the valid edge of the TImn pin input is detected (an external event), and then generate INTTMmn (a timer interrupt) after any specified interval. It is also possible to start counting down and generate INTTMmn (timer interrupt) at any interval by setting TSmn to 1 by software while TEmn = 1.
Page 257 RL78/G1D CHAPTER 7 TIMER ARRAY UNIT Figure 7-61. Example of Basic Timing of Operation as Delay Counter TSmn TEmn TImn FFFFH TCRmn 0000H TDRmn INTTMmn Remarks 1. m: Unit number (m = 0), n: Channel number (n = 0 to 7) 2.
Page 258 RL78/G1D CHAPTER 7 TIMER ARRAY UNIT Figure 7-62. Example of Set Contents of Registers to Delay Counter (1/2) (a) Timer mode register mn (TMRmn) TMRmn Note CKSmn1 CKSmn0 CCSmn STSmn2 STSmn1 STSmn0 CISmn1 CISmn0 MDmn3 MDmn2 MDmn1 MDmn0 Operation mode of channel n 100B: One-count mode Start trigger during operation 0: Trigger input is invalid.
Page 259 RL78/G1D CHAPTER 7 TIMER ARRAY UNIT Figure 7-62. Example of Set Contents of Registers to Delay Counter (2/2) (d) Timer output level register 0 (TOL0) Bit n TOL0 0: Cleared to 0 when TOM0n = 0 (master channel output mode). TOL0n (e) Timer output mode register 0 (TOM0) Bit n...
Page 260 RL78/G1D CHAPTER 7 TIMER ARRAY UNIT Figure 7-63. Operation Procedure When Delay Counter Function Is Used Software Operation Hardware Status Power-off status default (Clock supply is stopped and writing to each register is setting disabled.) Sets the TAUmEN bit of peripheral enable register 0 Power-on status.
Page 261: Simultaneous Channel Operation Function Of Timer Array Unit
RL78/G1D CHAPTER 7 TIMER ARRAY UNIT 7.9 Simultaneous Channel Operation Function of Timer Array Unit 7.9.1 Operation as one-shot pulse output function By using two channels as a set, a one-shot pulse having any delay pulse width can be generated from the signal input to the TImn pin.
Page 262 RL78/G1D CHAPTER 7 TIMER ARRAY UNIT Figure 7-64. Block Diagram of Operation as One-Shot Pulse Output Function Master channel (one-count mode) CKm1 Operation clock Timer counter register mn (TCRmn) CKm0 TNFEN0x TSmn Timer data Interrupt Interrupt signal register mn (TDRmn) controller Noise Edge...
Page 263 RL78/G1D CHAPTER 7 TIMER ARRAY UNIT Figure 7-65. Example of Basic Timing of Operation as One-Shot Pulse Output Function TSmn TEmn TImn Master FFFFH channel TCRmn 0000H TDRmn TO0n INTTMmn TSmp TEmp FFFFH TCRmp Slave 0000H channel TDRmp TO0p INTTMmp Remarks 1.
Page 264 RL78/G1D CHAPTER 7 TIMER ARRAY UNIT Figure 7-66. Example of Set Contents of Registers When One-Shot Pulse Output Function Is Used (Master Channel) (a) Timer mode register mn (TMRmn) TMRmn CKSmn1 CKSmn0 CCSmn STSmn2 STSmn1 STSmn0 CISmn1 CISmn0 MDmn3 MDmn2 MDmn1 MDmn0 TERmn...
Page 265 RL78/G1D CHAPTER 7 TIMER ARRAY UNIT Figure 7-67. Example of Set Contents of Registers When One-Shot Pulse Output Function Is Used (Slave Channel) (a) Timer mode register mp (TMRmp) TMRmp Note CKSmp1 CKSmp0 CCSmp STSmp2 STSmp1 STSmp0 CISmp1 CISmp0 MDmp3 MDmp2 MDmp1 MDmp0...
Page 266 RL78/G1D CHAPTER 7 TIMER ARRAY UNIT Figure 7-68. Operation Procedure of One-Shot Pulse Output Function (1/2) Software Operation Hardware Status Power-off status default (Clock supply is stopped and writing to each register is setting disabled.) Sets the TAUmEN bit of peripheral enable registers 0 Power-on status.
Page 267 RL78/G1D CHAPTER 7 TIMER ARRAY UNIT Figure 7-68. Operation Procedure of One-Shot Pulse Output Function (2/2) Software Operation Hardware Status Operation Sets the TOE0p bit (slave) to 1 (only when operation is start resumed). The TSmn (master) and TSmp (slave) bits of timer channel start register m (TSm) are set to 1 at the same time.
Page 268: Operation As Pwm Function
RL78/G1D CHAPTER 7 TIMER ARRAY UNIT 7.9.2 Operation as PWM function Two channels can be used as a set to generate a pulse of any period and duty factor. The period and duty factor of the output pulse can be calculated by the following expressions. Pulse period = {Set value of TDRmn (master) + 1} ×...
Page 269 RL78/G1D CHAPTER 7 TIMER ARRAY UNIT Figure 7-69. Block Diagram of Operation as PWM Function Master channel (interval timer mode) CKm1 Operation clock Timer counter register mn (TCRmn) CKm0 Timer data Interrupt Interrupt signal TSmn register mn (TDRmn) controller (INTTMmn) Slave channel (one-count mode) CKm1...
Page 270 RL78/G1D CHAPTER 7 TIMER ARRAY UNIT Figure 7-70. Example of Basic Timing of Operation as PWM Function TSmn TEmn FFFFH Master TCRmn channel 0000H TDRmn TO0n INTTMmn TSmp TEmp FFFFH TCRmp Slave 0000H channel TDRmp TO0p INTTMmp Remark 1. m: Unit number (m = 0), n: Master channel number (n = 0, 2, 4, 6) p: Slave channel number (n <...
Page 271 RL78/G1D CHAPTER 7 TIMER ARRAY UNIT Figure 7-71. Example of Set Contents of Registers When PWM Function (Master Channel) Is Used (a) Timer mode register mn (TMRmn) TMRmn CKSmn1 CKSmn0 CCSmn STSmn2 STSmn1 STSmn0 CISmn1 CISmn0 MDmn3 MDmn2 MDmn1 MDmn0 TERmn Note Operation mode of channel n...
Page 272 RL78/G1D CHAPTER 7 TIMER ARRAY UNIT Figure 7-72. Example of Set Contents of Registers When PWM Function (Slave Channel) Is Used (a) Timer mode register mp (TMRmp) TMRmp Note CKSmp1 CKSmp0 CCSmp STSmp2 STSmp1 STSmp0 CISmp1 CISmp0 MDmp3 MDmp2 MDmp1 MDmp0 Operation mode of channel p 100B: One-count mode...
Page 273 RL78/G1D CHAPTER 7 TIMER ARRAY UNIT Figure 7-73. Operation Procedure When PWM Function Is Used (1/2) Software Operation Hardware Status Power-off status default (Clock supply is stopped and writing to each register is setting disabled.) Sets the TAUmEN bit of peripheral enable register 0 Power-on status.
Page 274 RL78/G1D CHAPTER 7 TIMER ARRAY UNIT Figure 7-73. Operation Procedure When PWM Function Is Used (2/2) Software Operation Hardware Status Operation Sets the TOE0p bit (slave) to 1 (only when operation is start resumed). The TSmn (master) and TSmp (slave) bits of timer TEmn = 1, TEmp = 1 channel start register m (TSm) are set to 1 at the same When the master channel starts counting, INTTMmn is...
Page 275: Operation As Multiple Pwm Output Function
RL78/G1D CHAPTER 7 TIMER ARRAY UNIT 7.9.3 Operation as multiple PWM output function By extending the PWM function and using multiple slave channels, many PWM waveforms with different duty values can be output. For example, when using two slave channels, the period and duty factor of an output pulse can be calculated by the following expressions.
Page 276 RL78/G1D CHAPTER 7 TIMER ARRAY UNIT Figure 7-74. Block Diagram of Operation as Multiple PWM Output Function (output two types of PWMs) Master channel (interval timer mode) CKm1 Operation clock Timer counter register mn (TCRmn) CKm0 Timer data Interrupt Interrupt signal TSmn register mn (TDRmn) controller...
Page 277 RL78/G1D CHAPTER 7 TIMER ARRAY UNIT Figure 7-75. Example of Basic Timing of Operation as Multiple PWM Output Function (Output two types of PWMs) TSmn TEmn FFFFH Master TCRmn channel 0000H TDRmn TO0n INTTMmn TSmp TEmp FFFFH TCRmp Slave 0000H channel 1 TDRmp TO0p...
Page 278 RL78/G1D CHAPTER 7 TIMER ARRAY UNIT Remarks 1. m: Unit number (m = 0), n: Master channel number (n = 0, 2, 4) p: Slave channel number 1, q: Slave channel number 2 n < p < q 7 (Where p and q are integers greater than n) ≤...
Page 279 RL78/G1D CHAPTER 7 TIMER ARRAY UNIT Figure 7-76. Example of Set Contents of Registers When Multiple PWM Output Function (Master Channel) Is Used (a) Timer mode register mn (TMRmn) TMRmn CKSmn1 CKSmn0 CCSmn STSmn2 STSmn1 STSmn0 CISmn1 CISmn0 MDmn3 MDmn2 MDmn1 MDmn0 TERmn...
Page 280 RL78/G1D CHAPTER 7 TIMER ARRAY UNIT Figure 7-77. Example of Set Contents of Registers When Multiple PWM Output Function (Slave Channel) Is Used (output two types of PWMs) (a) Timer mode register mp, mq (TMRmp, TMRmq) TMRmp Note CKSmp1 CKSmp0 CCSmp STSmp2 STSmp1...
Page 281 RL78/G1D CHAPTER 7 TIMER ARRAY UNIT Figure 7-78. Operation Procedure When Multiple PWM Output Function Is Used (1/2) Software Operation Hardware Status Power-off status default (Clock supply is stopped and writing to each register is setting disabled.) Sets the TAUmEN bit of peripheral enable register 0 (PER0) to 1.
Page 282 RL78/G1D CHAPTER 7 TIMER ARRAY UNIT Figure 7-78. Operation Procedure When Multiple PWM Output Function Is Used (2/2) Software Operation Hardware Status Operation (Sets the TOE0p and TOE0q (slave) bits to 1 only when start resuming operation.) The TSmn bit (master), and TSmp and TSmq (slave) bits of timer channel start register m (TSm) are set to 1 at the TEmn = 1, TEmp, TEmq = 1 same time.
Page 283: Cautions When Using Timer Array Unit
RL78/G1D CHAPTER 7 TIMER ARRAY UNIT 7.10 Cautions When Using Timer Array Unit 7.10.1 Cautions when using timer output Pins may be assigned multiplexed timer output and other alternate functions. The assignment depends on the product. If you intend to use a timer output, set the outputs from all other multiplexed pin functions to their initial values. For details, see 5.5 Register Settings When Using Alternate Function.
Page 284: Chapter 8 Real-Time Clock
RL78/G1D CHAPTER 8 REAL-TIME CLOCK CHAPTER 8 REAL-TIME CLOCK 8.1 Functions of Real-time Clock The real-time clock has the following features. ● Having counters of year, month, week, day, hour, minute, and second, and can count up to 99 years. ●...
Page 285 RL78/G1D CHAPTER 8 REAL-TIME CLOCK Figure 8-1. Block Diagram of Real-time Clock Real-time clock control register 1 Real-time clock control register 0 Subsystem clock supply mode WUTMM WALE WALIE WAFG RIFG RWST RWAIT RTCE RCLOE1 AMPM control register (OSMC) RTC1HZ Alarm week Alarm hour Alarm minute...
Page 286: Registers Controlling Real-Time Clock
RL78/G1D CHAPTER 8 REAL-TIME CLOCK 8.3 Registers Controlling Real-time Clock The real-time clock is controlled by the following registers. ● Peripheral enable register 0 (PER0) ● Subsystem clock supply mode control register (OSMC) ● Real-time clock control register 0 (RTCC0) ●...
Page 287: Peripheral Enable Register 0 (Per0)
RL78/G1D CHAPTER 8 REAL-TIME CLOCK 8.3.1 Peripheral enable register 0 (PER0) This register is used to enable or disable supplying the clock to the peripheral hardware. Clock supply to a hardware macro that is not used is stopped in order to reduce the power consumption and noise. When the real-time clock is used, be sure to set bit 7 (RTCEN) of this register to 1.
Page 288: Subsystem Clock Supply Mode Control Register (Osmc)
RL78/G1D CHAPTER 8 REAL-TIME CLOCK 8.3.2 Subsystem clock supply mode control register (OSMC) The WUTMMCK0 bit can be used to select the count clock (f ) of the real-time clock. In addition, by stopping clock functions that are unnecessary, the RTCLPC bit can be used to reduce power consumption.
Page 289: Real-Time Clock Control Register 0 (Rtcc0)
RL78/G1D CHAPTER 8 REAL-TIME CLOCK 8.3.3 Real-time clock control register 0 (RTCC0) The RTCC0 register is an 8-bit register that is used to start or stop the real-time clock operation, control the RTC1HZ pin, and set a 12- or 24-hour system and the constant-period interrupt function. The RTCC0 register can be set by a 1-bit or 8-bit memory manipulation instruction.
Page 290: Real-Time Clock Control Register 1 (Rtcc1)
RL78/G1D CHAPTER 8 REAL-TIME CLOCK 8.3.4 Real-time clock control register 1 (RTCC1) The RTCC1 register is an 8-bit register that is used to control the alarm interrupt function and the wait time of the counter. The RTCC1 register can be set by a 1-bit or 8-bit memory manipulation instruction. Reset signal generation clears this register to 00H.
Page 291 RL78/G1D CHAPTER 8 REAL-TIME CLOCK Figure 8-5. Format of Real-time Clock Control Register 1 (RTCC1) (2/2) RWST Wait status flag of real-time clock Counter is operating. Mode to read or write counter value This status flag indicates whether the setting of the RWAIT bit is valid. Before reading or writing the counter value, confirm that the value of this flag is 1.
Page 292: Second Count Register (Sec)
RL78/G1D CHAPTER 8 REAL-TIME CLOCK 8.3.5 Second count register (SEC) The SEC register is an 8-bit register that takes a value of 0 to 59 (decimal) and indicates the count value of seconds. It counts up when the internal counter (16-bit) overflows. When data is written to this register, it is written to a buffer and then to the counter up to two cycles of f later.
Page 293: Hour Count Register (Hour)
RL78/G1D CHAPTER 8 REAL-TIME CLOCK 8.3.7 Hour count register (HOUR) The HOUR register is an 8-bit register that takes a value of 00 to 23 or 01 to 12 and 21 to 32 (decimal) and indicates the count value of hours. It counts up when the minute counter overflows.
Page 294 RL78/G1D CHAPTER 8 REAL-TIME CLOCK Table 8-2 shows the relationship between the setting value of the AMPM bit, the hour count register (HOUR) value, and time. Table 8-2. Displayed Time Digits 24-Hour Display (AMPM = 1) 12-Hour Display (AMPM = 0) Time HOUR Register Time...
Page 295: Day Count Register (Day)
RL78/G1D CHAPTER 8 REAL-TIME CLOCK 8.3.8 Day count register (DAY) The DAY register is an 8-bit register that takes a value of 1 to 31 (decimal) and indicates the count value of days. It counts up when the hour counter overflows. This counter counts as follows.
Page 296: Week Count Register (Week)
RL78/G1D CHAPTER 8 REAL-TIME CLOCK 8.3.9 Week count register (WEEK) The WEEK register is an 8-bit register that takes a value of 0 to 6 (decimal) and indicates the count value of weekdays. It counts up in synchronization with the day counter. When data is written to this register, it is written to a buffer and then to the counter up to two cycles of f later.
Page 297: Month Count Register (Month)
RL78/G1D CHAPTER 8 REAL-TIME CLOCK 8.3.10 Month count register (MONTH) The MONTH register is an 8-bit register that takes a value of 1 to 12 (decimal) and indicates the count value of months. It counts up when the day counter overflows. When data is written to this register, it is written to a buffer and then to the counter up to two cycles of f later.
Page 298: Watch Error Correction Register (Subcud)
RL78/G1D CHAPTER 8 REAL-TIME CLOCK 8.3.12 Watch error correction register (SUBCUD) This register is used to correct the watch with high accuracy when it is slow or fast by changing the value that overflows from the internal counter (16-bit) to the second count register (SEC) (reference value: 7FFFH). The SUBCUD register can be set by an 8-bit memory manipulation instruction.
Page 299: Alarm Minute Register (Alarmwm)
RL78/G1D CHAPTER 8 REAL-TIME CLOCK 8.3.13 Alarm minute register (ALARMWM) This register is used to set minutes of alarm. The ALARMWM register can be set by an 8-bit memory manipulation instruction. Reset signal generation clears this register to 00H. Caution Set a decimal value of 00 to 59 to this register in BCD code. If a value outside the range is set, the alarm is not detected.
Page 300: Alarm Week Register (Alarmww)
RL78/G1D CHAPTER 8 REAL-TIME CLOCK 8.3.15 Alarm week register (ALARMWW) This register is used to set date of alarm. The ALARMWW register can be set by an 8-bit memory manipulation instruction. Reset signal generation clears this register to 00H. Figure 8-16. Format of Alarm Week Register (ALARMWW) Address: FFF9CH After reset: 00H Symbol...
Page 301: Port Mode Register 3 (Pm3)
RL78/G1D CHAPTER 8 REAL-TIME CLOCK 8.3.16 Port mode register 3 (PM3) The PM3 register can be set by a 1-bit or 8-bit manipulation instruction. Reset signal generation sets this register to FFH. When using the port 3 as the RTC1HZ pin for output of 1 Hz, set the PM30 bit to 0. Figure 8-17.
Page 302: Real-Time Clock Operation
RL78/G1D CHAPTER 8 REAL-TIME CLOCK 8.4 Real-time Clock Operation 8.4.1 Starting operation of real-time clock Figure 8-19. Procedure for Starting Operation of Real-time Clock Start RTCEN = 1 Note 1 Supplies input clock. RTCE = 0 Stops counter operation. Sets f Setting WUTMMCK0 Setting AMPM, CT2 to CT0 Selects 12-/24-hour system and interrupt (INTRTC)
Page 303: Shifting To Halt/Stop Mode After Starting Operation
RL78/G1D CHAPTER 8 REAL-TIME CLOCK 8.4.2 Shifting to HALT/STOP mode after starting operation Perform one of the following processing when shifting to HALT/STOP mode immediately after setting the RTCE bit to 1. However, after setting the RTCE bit to 1, this processing is not required when shifting to HALT/STOP mode after the INTRTC interrupt has occurred.
Page 304: Reading/Writing Real-Time Clock
RL78/G1D CHAPTER 8 REAL-TIME CLOCK 8.4.3 Reading/writing real-time clock Read or write the counter after setting 1 to RWAIT first. Set RWAIT to 0 after completion of reading or writing the counter. Figure 8-21. Procedure for Reading Real-time Clock Start Stops SEC to YEAR counters.
Page 305 RL78/G1D CHAPTER 8 REAL-TIME CLOCK Figure 8-22. Procedure for Writing Real-time Clock Start Stops SEC to YEAR counters. RWAIT = 1 Mode to read and write count values RWST = 1? Checks wait status of counter. Writing SEC Writes second count register. Writing MIN Writes minute count register.
Page 306: Setting Alarm Of Real-Time Clock
RL78/G1D CHAPTER 8 REAL-TIME CLOCK 8.4.4 Setting alarm of real-time clock Set time of alarm after setting 0 to WALE (alarm operation invalid.) first. Figure 8-23. Alarm processing Procedure Start Match operation of alarm is invalid. WALE = 0 alarm match interrupts is valid.. WALIE = 1 Setting ALARMWM Sets alarm minute register.
Page 307: Hz Output Of Real-Time Clock
RL78/G1D CHAPTER 8 REAL-TIME CLOCK 8.4.5 1 Hz output of real-time clock Figure 8-24. 1 Hz Output Setting Procedure Start RTCE = 0 Stops counter operation. Sets P30 = 0 and PM30 = 0 Setting port RCLOE1 = 1 Enables output of the RTC1HZ pin (1 Hz). RTCE = 1 Starts counter operation.
Page 308: Example Of Watch Error Correction Of Real-Time Clock
RL78/G1D CHAPTER 8 REAL-TIME CLOCK 8.4.6 Example of watch error correction of real-time clock The watch can be corrected with high accuracy when it is slow or fast, by setting a value to the watch error correction register. Example of calculating the correction value The correction value used when correcting the count value of the internal counter (16-bit) is calculated by using the following expression.
Page 309 RL78/G1D CHAPTER 8 REAL-TIME CLOCK Correction example 1 Example of correcting from 32772.3 Hz to 32768 Hz (32772.3 Hz – 131.2 ppm) [Measuring the oscillation frequency] Note The oscillation frequency of each product is measured by outputting about 32.768 kHz from the PCLBUZ0 pin, or by outputting about 1 Hz from the RTC1HZ pin when the watch error correction register (SUBCUD) is set to its initial value (00H).
Page 310 RL78/G1D CHAPTER 8 REAL-TIME CLOCK R01UH0515EJ0120 Rev.1.20 Dec 16, 2016...
Page 311 RL78/G1D CHAPTER 8 REAL-TIME CLOCK Correction example 2 Example of correcting from 32767.4 Hz to 32768 Hz (32767.4 Hz + 18.3 ppm) [Measuring the oscillation frequency] Note The oscillation frequency of each product is measured by outputting about 1 Hz from the RTC1HZ pin when the watch error correction register (SUBCUD) is set to its initial value (00H).
Page 312 RL78/G1D CHAPTER 8 REAL-TIME CLOCK R01UH0515EJ0120 Rev.1.20 Dec 16, 2016...
Page 313: Chapter 9 12-Bit Interval Timer
RL78/G1D CHAPTER 9 12-BIT INTERVAL TIMER CHAPTER 9 12-BIT INTERVAL TIMER 9.1 Functions of 12-bit Interval Timer An interrupt (INTIT) is generated at any previously specified time interval. It can be utilized for wakeup from STOP mode and triggering an A/D converter’s SNOOZE mode. 9.2 Configuration of 12-bit Interval Timer The 12-bit interval timer includes the following hardware.
Page 314: Registers Controlling 12-Bit Interval Timer
RL78/G1D CHAPTER 9 12-BIT INTERVAL TIMER 9.3 Registers Controlling 12-bit Interval Timer The 12-bit interval timer is controlled by the following registers. ● Peripheral enable register 0 (PER0) ● Subsystem clock supply mode control register (OSMC) ● Interval timer control register (ITMC) 9.3.1 Peripheral enable register 0 (PER0) This register is used to enable or disable supplying the clock to the peripheral hardware.
Page 315: Subsystem Clock Supply Mode Control Register (Osmc)
RL78/G1D CHAPTER 9 12-BIT INTERVAL TIMER 9.3.2 Subsystem clock supply mode control register (OSMC) The WUTMMCK0 bit can be used to select the 12-bit interval timer or real-time clock operation clock. In addition, by stopping clock functions that are unnecessary, the RTCLPC bit can be used to reduce power consumption.
Page 316: Interval Timer Control Register (Itmc)
RL78/G1D CHAPTER 9 12-BIT INTERVAL TIMER 9.3.3 Interval timer control register (ITMC) This register is used to set up the starting and stopping of the 12-bit interval timer operation and to specify the timer compare value. The ITMC register can be set by a 16-bit memory manipulation instruction. Reset signal generation clears this register to 0FFFH.
Page 317: 12-Bit Interval Timer Operation
RL78/G1D CHAPTER 9 12-BIT INTERVAL TIMER 9.4 12-bit Interval Timer Operation 9.4.1 12-bit interval timer operation timing The count value specified for the ITMCMP11 to ITMCMP0 bits is used as an interval to operate an 12-bit interval timer that repeatedly generates interrupt requests (INTIT). When the RINTE bit is set to 1, the 12-bit counter starts counting.
Page 318: Start Of Count Operation And Re-Enter To Halt/Stop Mode After Returned From
RL78/G1D CHAPTER 9 12-BIT INTERVAL TIMER 9.4.2 Start of count operation and re-enter to HALT/STOP mode after returned from HALT/STOP mode When setting the RINTE bit after returned from HALT or STOP mode and entering HALT or STOP mode again, write 1 to the RINTE bit, and confirm the written value of the RINTE bit is reflected or wait for at least one cycle of the count clock.
Page 319: Chapter 10 Clock Output/Buzzer Output Controller
RL78/G1D CHAPTER 10 CLOCK OUTPUT/BUZZER OUTPUT CONTROLLER CHAPTER 10 CLOCK OUTPUT/BUZZER OUTPUT CONTROLLER Output pins of the clock output and buzzer output controllers are PCLBUZ0. 10.1 Functions of Clock Output/Buzzer Output Controller The clock output controller is intended for clock output for supply to peripheral ICs. Buzzer output is a function to output a square wave of buzzer frequency.
Page 320 RL78/G1D CHAPTER 10 CLOCK OUTPUT/BUZZER OUTPUT CONTROLLER Figure 10-1. Block Diagram of Clock Output/Buzzer Output Controller MAIN Prescaler to f MAIN MAIN to f MAIN MAIN Clock/buzzer Note PCLBUZ0 /INTP6/P140 controller to f PCLOE0 Output latch PM140 Prescaler (P140) PCLOE0 CSEL0 CCS02 CCS01 CCS00 Clock output select register 0 (CKS0) Internal bus...
Page 321: Configuration Of Clock Output/Buzzer Output Controller
RL78/G1D CHAPTER 10 CLOCK OUTPUT/BUZZER OUTPUT CONTROLLER 10.2 Configuration of Clock Output/Buzzer Output Controller The clock output/buzzer output controller includes the following hardware. Table 10-1. Configuration of Clock Output/Buzzer Output Controller Item Configuration Control registers Clock output select registers n (CKSn) Port mode register 14 (PM14) Port register 14 (P14) 10.3 Registers Controlling Clock Output/Buzzer Output Controller...
Page 322 RL78/G1D CHAPTER 10 CLOCK OUTPUT/BUZZER OUTPUT CONTROLLER Figure 10-2. Format of Clock Output Select Register n (CKSn) Address: FFFA5H (CKS0) After reset: 00H Symbol <7> CKSn PCLOEn CSELn CCSn2 CCSn1 CCSn0 PCLOEn PCLBUZn pin output enable/disable specification Output disable (default) Output enable CSELn CCSn2 CCSn1 CCSn0 PCLBUZn pin output clock selection...
Page 323: Registers Controlling Port Functions Of Pins To Be Used For Clock Or Buzzer Output
RL78/G1D CHAPTER 10 CLOCK OUTPUT/BUZZER OUTPUT CONTROLLER 10.3.2 Registers controlling port functions of pins to be used for clock or buzzer output Using a port pin for clock or buzzer output requires setting of the registers that control the port functions multiplexed on the target pin (port mode register (PMxx), port register (Pxx)).
Page 324: Operations Of Clock Output/Buzzer Output Controller
RL78/G1D CHAPTER 10 CLOCK OUTPUT/BUZZER OUTPUT CONTROLLER 10.4 Operations of Clock Output/Buzzer Output Controller One pin can be used to output a clock or buzzer sound. The PCLBUZ0 pin outputs a clock/buzzer selected by the clock output select register 0 (CKS0). 10.4.1 Operation as output pin The PCLBUZn pin is output as the following procedure.
Page 325: Chapter 11 Watchdog Timer
RL78/G1D CHAPTER 11 WATCHDOG TIMER CHAPTER 11 WATCHDOG TIMER 11.1 Functions of Watchdog Timer The counting operation of the watchdog timer is set by the option byte (000C0H). The watchdog timer operates on the low-speed on-chip oscillator clock (f The watchdog timer is used to detect an inadvertent program loop. If a program loop is detected, an internal reset signal is generated.
Page 326: Configuration Of Watchdog Timer
RL78/G1D CHAPTER 11 WATCHDOG TIMER 11.2 Configuration of Watchdog Timer The watchdog timer includes the following hardware. Table 11-1. Configuration of Watchdog Timer Item Configuration Counter Internal counter (17 bits) Control register Watchdog timer enable register (WDTE) How the counter operation is controlled, overflow time, window open period, and interval interrupt are set by the option byte.
Page 327: Register Controlling Watchdog Timer
RL78/G1D CHAPTER 11 WATCHDOG TIMER 11.3 Register Controlling Watchdog Timer The watchdog timer is controlled by the watchdog timer enable register (WDTE). 11.3.1 Watchdog timer enable register (WDTE) Writing “ACH” to the WDTE register clears the watchdog timer counter and starts counting again. This register can be set by an 8-bit memory manipulation instruction.
Page 328: Operation Of Watchdog Timer
RL78/G1D CHAPTER 11 WATCHDOG TIMER 11.4 Operation of Watchdog Timer 11.4.1 Controlling operation of watchdog timer (1) When the watchdog timer is used, its operation is specified by the option byte (000C0H). ● Enable counting operation of the watchdog timer by setting bit 4 (WDTON) of the option byte (000C0H) to 1 (the counter starts operating after a reset release) (for details, see CHAPTER 25).
Page 329: Setting Overflow Time Of Watchdog Timer
RL78/G1D CHAPTER 11 WATCHDOG TIMER Cautions 4. The operation of the watchdog timer in the HALT, STOP, and SNOOZE modes differs as follows depending on the set value of bit 0 (WDSTBYON) of the option byte (000C0H). WDSTBYON = 0 WDSTBYON = 1 In HALT mode Watchdog timer operation stops.
Page 330: Setting Window Open Period Of Watchdog Timer
RL78/G1D CHAPTER 11 WATCHDOG TIMER 11.4.3 Setting window open period of watchdog timer Set the window open period of the watchdog timer by using bits 6 and 5 (WINDOW1, WINDOW0) of the option byte (000C0H). The outline of the window is as follows. ●...
Page 331 RL78/G1D CHAPTER 11 WATCHDOG TIMER Table 11-4. Setting Window Open Period of Watchdog Timer WINDOW1 WINDOW0 Window Open Period of Watchdog Timer Setting prohibited Note 100% <R> Note When the window open period is set to 75%, clearing the counter of the watchdog timer (writing ACH to WDTE) must proceed outside the corresponding period from among those listed below, over which clearing of the counter is prohibited (for example, confirming that the interval timer interrupt request flag (WDTIIF) of the watchdog timer is set).
Page 332: Setting Watchdog Timer Interval Interrupt
RL78/G1D CHAPTER 11 WATCHDOG TIMER 11.4.4 Setting watchdog timer interval interrupt Depending on the setting of bit 7 (WDTINT) of an option byte (000C0H), an interval interrupt (INTWDTI) can be generated when 75% + 1/2f of the overflow time is reached. Table 11-5.
Page 333: Chapter 12 A/D Converter
RL78/G1D CHAPTER 12 A/D CONVERTER CHAPTER 12 A/D CONVERTER 12.1 Function of A/D Converter The A/D converter is used to convert analog input signals into digital values, and is configured to control analog inputs, including 8 channels of A/D converter analog inputs (ANI0 to ANI3 and ANI16 to ANI19). 10-bit or 8-bit resolution can be selected by the ADTYP bit of the A/D converter mode register 2 (ADM2).
Page 334 RL78/G1D CHAPTER 12 A/D CONVERTER R01UH0515EJ0120 Rev.1.20 Dec 16, 2016...
Page 335: Configuration Of A/D Converter
RL78/G1D CHAPTER 12 A/D CONVERTER 12.2 Configuration of A/D Converter The A/D converter includes the following hardware. (1) ANI0 to ANI3 and ANI16 to ANI19 pins These are the analog input pins of the 8 channels of the A/D converter. They input analog signals to be converted into digital signals.
Page 336 RL78/G1D CHAPTER 12 A/D CONVERTER (5) Successive approximation register (SAR) The SAR register is a register that sets voltage tap data whose values from the comparison voltage generator match the voltage values of the analog input pins, 1 bit at a time starting from the most significant bit (MSB). If data is set in the SAR register all the way to the least significant bit (LSB) (end of A/D conversion), the contents of the SAR register (conversion results) are held in the A/D conversion result register (ADCR).
Page 337: Registers Controlling A/D Converter
RL78/G1D CHAPTER 12 A/D CONVERTER 12.3 Registers Controlling A/D Converter The A/D converter is controlled by the following registers. ● Peripheral enable register 0 (PER0) ● A/D converter mode register 0 (ADM0) ● A/D converter mode register 1 (ADM1) ● A/D converter mode register 2 (ADM2) ●...
Page 338: Peripheral Enable Register 0 (Per0)
RL78/G1D CHAPTER 12 A/D CONVERTER 12.3.1 Peripheral enable register 0 (PER0) This register is used to enable or disable supplying the clock to the peripheral hardware. Clock supply to a hardware macro that is not used is stopped in order to reduce the power consumption and noise. When the A/D converter is used, be sure to set bit 5 (ADCEN) of this register to 1.
Page 339: A/D Converter Mode Register 0 (Adm0)
RL78/G1D CHAPTER 12 A/D CONVERTER 12.3.2 A/D converter mode register 0 (ADM0) This register sets the conversion time for analog input to be A/D converted, and starts/stops conversion. The ADM0 register can be set by a 1-bit or 8-bit memory manipulation instruction. Reset signal generation clears this register to 00H.
Page 340 RL78/G1D CHAPTER 12 A/D CONVERTER Table 12-1. Settings of ADCS and ADCE Bits ADCS ADCE A/D Conversion Operation Conversion stopped state Conversion standby state Setting prohibited Conversion-in-progress state Table 12-2. Setting and Clearing Conditions for ADCS Bit A/D Conversion Mode Set Conditions Clear Conditions Software...
Page 341 RL78/G1D CHAPTER 12 A/D CONVERTER Figure 12-4. Timing Chart When A/D Voltage Comparator Is Used A/D voltage comparator: enables operation ADCE A/D voltage comparator Conversion start time Note 2 Conversion Conversion Conversion Conversion operation standby stopped standby Software ADCS Note 1 trigger mode 1 is written 0 is written to ADCS.
Page 342 RL78/G1D CHAPTER 12 A/D CONVERTER Cautions 1. If using the hardware trigger wait mode, setting the ADCS bit to 1 is prohibited (but the bit is automatically switched to 1 when the hardware trigger signal is detected). However, it is possible to clear the ADCS bit to 0 to specify the A/D conversion standby status.
Page 343 RL78/G1D CHAPTER 12 A/D CONVERTER Table 12-3. A/D Conversion Time Selection (1/4) (1) When there is no A/D power supply stabilization wait time Normal mode 1, 2 (software trigger mode/hardware trigger no-wait mode) A/D Converter Mode Register 0 Mode Conversion Number of Conversion Conversion Time at 10-Bit Resolution...
Page 344 RL78/G1D CHAPTER 12 A/D CONVERTER Table 12-3. A/D Conversion Time Selection (2/4) (2) When there is no A/D power supply stabilization wait time Low-voltage mode 1, 2 (software trigger mode/hardware trigger no-wait mode) A/D Converter Mode Register 0 Mode Conversion Number of Conversion Conversion Time at 10-Bit Resolution...
Page 345 RL78/G1D CHAPTER 12 A/D CONVERTER Table 12-3. A/D Conversion Time Selection (3/4) (3) When there is A/D power supply stabilization wait time Note 1 Normal mode 1, 2 (hardware trigger wait mode A/D Converter Mode Mode Conversion Number of Number of A/D Power A/D Power Supply Stabilization Wait Time + Register 0 (ADM0)
Page 346 RL78/G1D CHAPTER 12 A/D CONVERTER Table 12-3. A/D Conversion Time Selection (4/4) (4) When there is no A/D power supply stabilization wait time Note 1 Low-voltage mode 1, 2 (hardware trigger wait mode A/D Converter Mode Register 0 Mode Conversion Number of Number of A/D Power...
Page 347 RL78/G1D CHAPTER 12 A/D CONVERTER Figure 12-5. A/D Converter Sampling and A/D Conversion Timing (Example for Software Trigger Mode) 1 is written to ADCS or ADS is rewritten. ADCS Sampling timing INTAD Sampling Sampling Successive conversion Successive conversion Conversion start Conversion Conversion time Conversion time...
Page 348: A/D Converter Mode Register 1 (Adm1)
RL78/G1D CHAPTER 12 A/D CONVERTER 12.3.3 A/D converter mode register 1 (ADM1) This register is used to specify the A/D conversion trigger, conversion mode, and hardware trigger signal. The ADM1 register can be set by a 1-bit or 8-bit memory manipulation instruction. Reset signal generation clears this register to 00H.
Page 349 RL78/G1D CHAPTER 12 A/D CONVERTER 12.3.4 A/D converter mode register 2 (ADM2) This register is used to select the A/D converter reference voltage, check the upper limit and lower limit A/D conversion result values, select the resolution, and specify whether to use the SNOOZE mode. The ADM2 register can be set by a 1-bit or 8-bit memory manipulation instruction.
Page 350 RL78/G1D CHAPTER 12 A/D CONVERTER Figure 12-7. Format of A/D Converter Mode Register 2 (ADM2) (2/2) Address: F0010H After reset: 00H Symbol <3> <2> <0> ADM2 ADREFP1 ADREFP0 ADREFM ADRCK ADTYP ADRCK Checking the upper limit and lower limit conversion result values The interrupt signal (INTAD) is output when the ADLL register ≤...
Page 351 RL78/G1D CHAPTER 12 A/D CONVERTER Figure 12-8. ADRCK Bit Interrupt Signal Generation Range ADCR register value (A/D conversion result) 1111111111 AREA 3 INTAD is generated (ADUL < ADCR) when ADRCK = 1. ADUL register setting AREA 1 INTAD is generated (ADLL £...
Page 352 RL78/G1D CHAPTER 12 A/D CONVERTER 12.3.6 8-bit A/D conversion result register (ADCRH) This register is an 8-bit register that stores the A/D conversion result. The higher 8 bits of 10-bit resolution are Note stored The ADCRH register can be read by an 8-bit memory manipulation instruction. Reset signal generation clears this register to 00H.
Page 353 RL78/G1D CHAPTER 12 A/D CONVERTER 12.3.7 Analog input channel specification register (ADS) This register specifies the input channel of the analog voltage to be A/D converted. The ADS register can be set by a 1-bit or 8-bit memory manipulation instruction. Reset signal generation clears this register to 00H.
Page 354 RL78/G1D CHAPTER 12 A/D CONVERTER Cautions 8. If the ADISS bit is set to 1, the internal reference voltage (1.45 V) cannot be used for the + side reference voltage. After the ADISS bit is set to 1, the initial conversion result cannot be used.
Page 355 RL78/G1D CHAPTER 12 A/D CONVERTER 12.3.8 Conversion result comparison upper limit setting register (ADUL) This register is used to specify the setting for checking the upper limit of the A/D conversion results. The A/D conversion results and ADUL register value are compared, and interrupt signal (INTAD) generation is controlled in the range specified for the ADRCK bit of A/D converter mode register 2 (ADM2) (shown in Figure 12-8).
Page 356 RL78/G1D CHAPTER 12 A/D CONVERTER 12.3.10 A/D test register (ADTES) This register is used to select the + side reference voltage or - side reference voltage for the converter, an analog input channel (ANIxx), the temperature sensor output voltage, or the internal reference voltage (1.45 V) as the target for A/D conversion.
Page 357 RL78/G1D CHAPTER 12 A/D CONVERTER 12.3.11 Registers controlling port function of analog input pins Set up the registers for controlling the functions of the ports shared with the analog input pins of the A/D converter (port mode registers (PMxx), port mode control registers (PMCxx), and A/D port configuration register (ADPC)). For details, see 5.3.1 Port mode registers (PMxx), 5.3.6 Port mode control registers (PMCxx), and 5.3.7...
Page 358 RL78/G1D CHAPTER 12 A/D CONVERTER 12.4 A/D Converter Conversion Operations The A/D converter conversion operations are described below. <1> The voltage input to the selected analog input channel is sampled by the sample & hold circuit. <2> When sampling has been done for a certain time, the sample & hold circuit is placed in the hold state and the sampled voltage is held until the A/D conversion operation has ended.
Page 359 RL78/G1D CHAPTER 12 A/D CONVERTER Figure 12-15. Conversion Operation of A/D Converter (Software Trigger Mode) 1 is written to ADCS ADCS Conversion time Conversion Sampling start time time Conversion Conversion Sampling A/D converter Conversion standby A/D conversion start operation standby Conversion Undefined result...
Page 360 RL78/G1D CHAPTER 12 A/D CONVERTER 12.5 Input Voltage and Conversion Results The relationship between the analog input voltage input to the analog input pins (ANI0 to ANI3 and ANI16 to ANI19) and the theoretical A/D conversion result (stored in the 10-bit A/D conversion result register (ADCR)) is shown by the following expression.
Page 361 RL78/G1D CHAPTER 12 A/D CONVERTER 12.6 A/D Converter Operation Modes The operation of each A/D converter mode is described below. In addition, the procedure for specifying each mode is described in 12.7 A/D Converter Setup Flowchart. 12.6.1 Software trigger mode (select mode, sequential conversion mode) <1>...
Page 362 RL78/G1D CHAPTER 12 A/D CONVERTER 12.6.2 Software trigger mode (select mode, one-shot conversion mode) <1> In the stop status, the ADCE bit of A/D converter mode register 0 (ADM0) is set to 1, and the system enters the A/D conversion standby status. <2>...
Page 363 RL78/G1D CHAPTER 12 A/D CONVERTER 12.6.3 Software trigger mode (scan mode, sequential conversion mode) <1> In the stop status, the ADCE bit of A/D converter mode register 0 (ADM0) is set to 1, and the system enters the A/D conversion standby status. <2>...
Page 364 RL78/G1D CHAPTER 12 A/D CONVERTER 12.6.4 Software trigger mode (scan mode, one-shot conversion mode) <1> In the stop status, the ADCE bit of A/D converter mode register 0 (ADM0) is set to 1, and the system enters the A/D conversion standby status. <2>...
Page 365 RL78/G1D CHAPTER 12 A/D CONVERTER 12.6.5 Hardware trigger no-wait mode (select mode, sequential conversion mode) <1> In the stop status, the ADCE bit of A/D converter mode register 0 (ADM0) is set to 1, and the system enters the A/D conversion standby status. <2>...
Page 366 RL78/G1D CHAPTER 12 A/D CONVERTER 12.6.6 Hardware trigger no-wait mode (select mode, one-shot conversion mode) <1> In the stop status, the ADCE bit of A/D converter mode register 0 (ADM0) is set to 1, and the system enters the A/D conversion standby status. <2>...
Page 367 RL78/G1D CHAPTER 12 A/D CONVERTER 12.6.7 Hardware trigger no-wait mode (scan mode, sequential conversion mode) <1> In the stop status, the ADCE bit of A/D converter mode register 0 (ADM0) is set to 1, and the system enters the A/D conversion standby status. <2>...
Page 368 RL78/G1D CHAPTER 12 A/D CONVERTER 12.6.8 Hardware trigger no-wait mode (scan mode, one-shot conversion mode) <1> In the stop status, the ADCE bit of A/D converter mode register 0 (ADM0) is set to 1, and the system enters the A/D conversion standby status. <2>...
Page 369 RL78/G1D CHAPTER 12 A/D CONVERTER 12.6.9 Hardware trigger wait mode (select mode, sequential conversion mode) <1> In the stop status, the ADCE bit of A/D converter mode register 0 (ADM0) is set to 1, and the system enters the hardware trigger standby status. <2>...
Page 370 RL78/G1D CHAPTER 12 A/D CONVERTER 12.6.10 Hardware trigger wait mode (select mode, one-shot conversion mode) <1> In the stop status, the ADCE bit of A/D converter mode register 0 (ADM0) is set to 1, and the system enters the hardware trigger standby status. <2>...
Page 371 RL78/G1D CHAPTER 12 A/D CONVERTER 12.6.11 Hardware trigger wait mode (scan mode, sequential conversion mode) <1> In the stop status, the ADCE bit of A/D converter mode register 0 (ADM0) is set to 1, and the system enters the A/D conversion standby status. <2>...
Page 372 RL78/G1D CHAPTER 12 A/D CONVERTER 12.6.12 Hardware trigger wait mode (scan mode, one-shot conversion mode) <1> In the stop status, the ADCE bit of A/D converter mode register 0 (ADM0) is set to 1, and the system enters the A/D conversion standby status. <2>...
Page 373 RL78/G1D CHAPTER 12 A/D CONVERTER 12.7 A/D Converter Setup Flowchart The A/D converter setup flowchart in each operation mode is described below. 12.7.1 Setting up software trigger mode Figure 12-29. Setting up Software Trigger Mode Start of setup PER0 register setting The ADCEN bit of the PER0 register is set (1), and supplying the clock starts.
Page 374 RL78/G1D CHAPTER 12 A/D CONVERTER 12.7.2 Setting up hardware trigger no-wait mode Figure 12-30. Setting up Hardware Trigger No-Wait Mode Start of setup The ADCEN bit of the PER0 register is set (1), and supplying the clock starts. PER0 register setting The ports are set to analog input.
Page 375 RL78/G1D CHAPTER 12 A/D CONVERTER 12.7.3 Setting up hardware trigger wait mode Figure 12-31. Setting up Hardware Trigger Wait Mode Start of setup The ADCEN bit of the PER0 register is set (1), and supplying the clock starts. PER0 register setting The ports are set to analog input.
Page 376 RL78/G1D CHAPTER 12 A/D CONVERTER 12.7.4 Setup when temperature sensor output/internal reference voltage output is selected (example for software trigger mode and one-shot conversion mode) Figure 12-32. Setup when temperature sensor output/internal reference voltage output is selected Start of setup The ADCEN bit of the PER0 register is set (1), and supplying the clock PER0 register setting starts.
Page 377 RL78/G1D CHAPTER 12 A/D CONVERTER 12.7.5 Setting up test mode Figure 12-33. Setting up Test Trigger Mode Start of setup PER0 register setting The ADCEN bit of the PER0 register is set (1), and supplying the clock starts. ● ADM0 register FR2 to FR0, LV1, and LV0 bits: These are used to specify the A/D conversion time.
Page 378 RL78/G1D CHAPTER 12 A/D CONVERTER 12.8 SNOOZE Mode Function In the SNOOZE mode, A/D conversion is triggered by inputting a hardware trigger in the STOP mode. Normally, A/D conversion is stopped while in the STOP mode, but, by using the SNOOZE mode, A/D conversion can be performed without operating the CPU by inputting a hardware trigger.
Page 379 RL78/G1D CHAPTER 12 A/D CONVERTER (1) If an interrupt is generated after A/D conversion ends If the A/D conversion result value is inside the range of values specified by the A/D conversion result comparison function (which is set up by using the ADRCK bit and ADUL/ADLL register), the A/D conversion end interrupt request signal (INTAD) is generated.
Page 380 RL78/G1D CHAPTER 12 A/D CONVERTER Figure 12-36. Operation Example When No Interrupt Is Generated After A/D Conversion Ends (While in Scan Mode) INTRTC Clock request signal (internal signal) The clock request signal ADCS is set to the low level. Conversion Channel 1 Channel 2 Channel 3...
Page 381 RL78/G1D CHAPTER 12 A/D CONVERTER Figure 12-37. Flowchart for Setting up SNOOZE Mode Start of setup The ADCEN bit of the PER0 register is set (1), and supplying the clock starts. PER0 register setting The ports are set to analog input. ADPC and PMCx ANI0 to ANI3 pins: Set using theADPC register register settings...
Page 382 RL78/G1D CHAPTER 12 A/D CONVERTER 12.9 How to Read A/D Converter Characteristics Table Here, special terms unique to the A/D converter are explained. (1) Resolution This is the minimum analog input voltage that can be identified. That is, the percentage of the analog input voltage per bit of digital output is called 1LSB (Least Significant Bit).
Page 383 RL78/G1D CHAPTER 12 A/D CONVERTER (5) Full-scale error This shows the difference between the actual measurement value of the analog input voltage and the theoretical value (Full-scale – 3/2LSB) when the digital output changes from 1..110 to 1..111. (6) Integral linearity error This shows the degree to which the conversion characteristics deviate from the ideal linear relationship.
Page 384 RL78/G1D CHAPTER 12 A/D CONVERTER 12.10 Cautions for A/D Converter (1) Operating current in STOP mode Shift to STOP mode after stopping the A/D converter (by setting bit 7 (ADCS) of A/D converter mode register 0 (ADM0) to 0). The operating current can be reduced by setting bit 0 (ADCE) of the ADM0 register to 0 at the same time.
Page 385 RL78/G1D CHAPTER 12 A/D CONVERTER Figure 12-44. Analog Input Pin Connection If there is a possibility that noise equal to or higher than AV REFP or equal to or lower than AV and V may enter, clamp with REFM a diode with a small V value (0.3 V or lower).
Page 386 RL78/G1D CHAPTER 12 A/D CONVERTER (7) Interrupt request flag (ADIF) The interrupt request flag (ADIF) is not cleared even if the analog input channel specification register (ADS) is changed. Therefore, if an analog input pin is changed during A/D conversion, the A/D conversion result and ADIF flag for the pre-change analog input may be set just before the ADS register rewrite.
Page 387 RL78/G1D CHAPTER 12 A/D CONVERTER (10) Internal equivalent circuit The equivalent circuit of the analog input block is shown below. Figure 12-46. Internal Equivalent Circuit of ANIn Pin ANIn Table 12-4. Resistance and Capacitance Values of Equivalent Circuit (Reference Values) ANIn Pin R1 [kΩ] C1 [pF]...
Page 388 RL78/G1D CHAPTER 13 SERIAL ARRAY UNIT CHAPTER 13 SERIAL ARRAY UNIT Serial array unit has up to four serial channels. Each channel can achieve 3-wire serial (CSI), UART, and simplified C communication. Function assignment of each channel supported by the RL78/G1D is as shown below. Used as Simplified I Unit Channel...
Page 389 RL78/G1D CHAPTER 13 SERIAL ARRAY UNIT 13.1 Functions of Serial Array Unit Each serial interface supported by the RL78/G1D has the following features. 13.1.1 3-wire serial I/O (CSI00, CSI20, CSI21) Data is transmitted or received in synchronization with the serial clock (SCK) output from the master channel. 3-wire serial communication is clocked communication performed by using three communication lines: one for the serial clock (SCK), one for transmitting serial data (SO), one for receiving serial data (SI).
Page 390 RL78/G1D CHAPTER 13 SERIAL ARRAY UNIT 13.1.2 UART (UART0, UART1) This is a start-stop synchronization function using two lines: serial data transmission (T D) and serial data reception D) lines. By using these two communication lines, each data frame, which consist of a start bit, data, parity bit, and stop bit, is transferred asynchronously (using the internal baud rate) between the microcontroller and the other communication party.
Page 391 RL78/G1D CHAPTER 13 SERIAL ARRAY UNIT 13.1.3 Simplified I C (IIC00, IIC20) This is a clocked communication function to communicate with two or more devices by using two lines: serial clock (SCL) and serial data (SDA). This simplified I C is designed for single communication with a device such as EEPROM, flash memory, or A/D converter, and therefore, it functions only as a master.
Page 392 RL78/G1D CHAPTER 13 SERIAL ARRAY UNIT 13.2 Configuration of Serial Array Unit The serial array unit includes the following hardware. Table 13-1. Configuration of Serial Array Unit Item Configuration Note 1 Shift register 8 bits or 9 bits Notes 1, 2 Buffer register Lower 8 bits or 9 bits of serial data register mn (SDRmn) SCK00, SCK20 pins (for 3-wire serial I/O), SCL00, SCL20 pins (for simplified I...
Page 393 RL78/G1D CHAPTER 13 SERIAL ARRAY UNIT Figure 13-1 shows the block diagram of serial array unit 0. Figure 13-1. Block Diagram of Serial Array Unit 0 Noise filter enable Serial output register 0 (SO0) register 0 (NFEN0) SNFEN SNFEN CKO02 SO02 CKO00 SO00...
Page 394 RL78/G1D CHAPTER 13 SERIAL ARRAY UNIT Figure 13-2 shows the block diagram of serial array unit 1. Figure 13-2. Block Diagram of Serial Array Unit 1 Serial output register 1 (SO1) SO11 SO10 CKO11 CKO10 Peripheral enable Serial channel register 0 (PER0) Serial clock select register 1 (SPS1) enable status SE11...
Page 395 RL78/G1D CHAPTER 13 SERIAL ARRAY UNIT 13.2.1 Shift register This is a 9-bit register that converts parallel data into serial data or vice versa. Note 1 In case of the UART communication of nine bits of data, nine bits (bits 0 to 8) are used During reception, it converts data input to the serial pin into parallel data.
Page 396 RL78/G1D CHAPTER 13 SERIAL ARRAY UNIT Figure 13-3. Format of Serial Data Register mn (SDRmn) (mn = 00, 01) Address: FFF10H, FFF11H (SDR00), FFF12H, FFF13H (SDR01) After reset: 0000H FFF11H (SDR00) FFF10H (SDR00) SDRmn Shift register Remark For the function of the higher 7 bits of the SDRmn register, see 13.3 Registers Controlling Serial Array Unit.
Page 397 RL78/G1D CHAPTER 13 SERIAL ARRAY UNIT 13.3 Registers Controlling Serial Array Unit Serial array unit is controlled by the following registers. ● Peripheral enable register 0 (PER0) ● Serial clock select register m (SPSm) ● Serial mode register mn (SMRmn) ●...
Page 398 RL78/G1D CHAPTER 13 SERIAL ARRAY UNIT 13.3.1 Peripheral enable register 0 (PER0) PER0 is used to enable or disable supplying the clock to the peripheral hardware. Clock supply to a hardware macro that is not used is stopped in order to reduce the power consumption and noise. When serial array unit 0 is used, be sure to set bit 2 (SAU0EN) of this register to 1.
Page 399 RL78/G1D CHAPTER 13 SERIAL ARRAY UNIT 13.3.2 Serial clock select register m (SPSm) The SPSm register is a 16-bit register that is used to select two types of operation clocks (CKm0, CKm1) that are commonly supplied to each channel. CKm1 is selected by bits 7 to 4 of the SPSm register , and CKm0 is selected by bits 3 to 0.
Page 400 RL78/G1D CHAPTER 13 SERIAL ARRAY UNIT 13.3.3 Serial mode register mn (SMRmn) The SMRmn register is a register that sets an operation mode of channel n. It is also used to select an operation clock ), specify whether the serial clock (f ) may be input or not, set a start trigger, an operation mode (CSI, UART, or simplified I C), and an interrupt source.
Page 401 RL78/G1D CHAPTER 13 SERIAL ARRAY UNIT Figure 13-7. Format of Serial Mode Register mn (SMRmn) (2/2) Address: F0110H, F0111H (SMR00) to F0116H, F0117H (SMR03), After reset: 0020H F0150H, F0151H (SMR10), F0152H, F0153H (SMR11) Symbol SMRmn Note Controls inversion of level of receive data of channel n in UART mode Note Falling edge is detected as the start bit.
Page 402 RL78/G1D CHAPTER 13 SERIAL ARRAY UNIT Figure 13-8. Format of Serial Communication Operation Setting Register mn (SCRmn) (1/2) Address: F0118H, F0119H (SCR00) to F011EH, F011FH (SCR03), After reset: 0087H F0158H, F0159H (SCR10), F015AH, F015BH (SMR11) Symbol SCRmn SLCm DLSm Note 1 Note 2 TXEmn RXEmn...
Page 403 RL78/G1D CHAPTER 13 SERIAL ARRAY UNIT Figure 13-8. Format of Serial Communication Operation Setting Register mn (SCRmn) (2/2) Address: F0118H, F0119H (SCR00) to F011EH, F011FH (SCR03), After reset: 0087H F0158H, F0159H (SCR10), F015AH, F015BH (SMR11) Symbol SCRmn SLCm DLSm Note 1 Note 2 PTCmn1 PTCmn0...
Page 404 RL78/G1D CHAPTER 13 SERIAL ARRAY UNIT 13.3.5 Higher 7 bits of the serial data register mn (SDRmn) The SDRmn register is the transmit/receive data register (16 bits) of channel n. Bits 8 to 0 (lower 9 bits) of SDR00, SDR01 or bits 7 to 0 (lower 8 bits) of SDR02, SDR03, SDR10, SDR11 function as a transmit/receive buffer register, and bits 15 to 9 (higher 7 bits) are used as a register that sets the division ratio of the operation clock (f If the CCSmn bit of serial mode register mn (SMRmn) is cleared to 0, the clock set by dividing the operation clock by bits 15 to 9 (higher 7 bits) of the SDRmn register is used as the transfer clock.
Page 405 RL78/G1D CHAPTER 13 SERIAL ARRAY UNIT Figure 13-9. Format of Serial Data Register mn (SDRmn) Address: FFF10H, FFF11H (SDR00), FFF12H, FFF13H (SDR01) After reset: 0000H FFF10H (SDR00) FFF11H (SDR00) Symbol SDRmn Address: FFF44H, FFF45H (SDR02), FFF46H, FFF47H (SDR03), After reset: 0000H FFF48H, FFF49H (SDR10), FFF4AH, FFF4BH (SDR11) FFF45H (SDR02) FFF44H (SDR02)
Page 406 RL78/G1D CHAPTER 13 SERIAL ARRAY UNIT 13.3.6 Serial flag clear trigger register mn (SIRmn) The SIRmn register is a trigger register that is used to clear each error flag of channel n. When each bit (FECTmn, PECTmn, OVCTmn) of this register is set to 1, the corresponding bit (FEFmn, PEFmn, OVFmn) of serial status register mn is cleared to 0.
Page 407 RL78/G1D CHAPTER 13 SERIAL ARRAY UNIT 13.3.7 Serial status register mn (SSRmn) The SSRmn register is a register that indicates the communication status and error occurrence status of channel n. The errors indicated by this register are a framing error, parity error, and overrun error. The SSRmn register can be read by a 16-bit memory manipulation instruction.
Page 408 RL78/G1D CHAPTER 13 SERIAL ARRAY UNIT Figure 13-11. Format of Serial Status Register mn (SSRmn) (2/2) Address: F0100H, F0101H (SSR00) to F0106H, F0107H (SSR03), After reset: 0000H F0140H, F0141H (SSR10), F0142H, F0143H (SSR11) Symbol SSRmn FEFm Note Note FEFmn Framing error detection flag of channel n No error occurs.
Page 409 RL78/G1D CHAPTER 13 SERIAL ARRAY UNIT 13.3.8 Serial channel start register m (SSm) The SSm register is a trigger register that is used to enable starting communication/count by each channel. When 1 is written a bit of this register (SSmn), the corresponding bit (SEmn) of serial channel enable status register m (SEm) is set to 1 (Operation is enabled).
Page 410 RL78/G1D CHAPTER 13 SERIAL ARRAY UNIT 13.3.9 Serial channel stop register m (STm) The STm register is a trigger register that is used to enable stopping communication/count by each channel. When 1 is written a bit of this register (STmn), the corresponding bit (SEmn) of serial channel enable status register m (SEm) is cleared to 0 (operation is stopped).
Page 411 RL78/G1D CHAPTER 13 SERIAL ARRAY UNIT 13.3.10 Serial channel enable status register m (SEm) The SEm register indicates whether data transmission/reception operation of each channel is enabled or stopped. When 1 is written a bit of serial channel start register m (SSm), the corresponding bit of this register is set to 1. When 1 is written a bit of serial channel stop register m (STm), the corresponding bit is cleared to 0.
Page 412 RL78/G1D CHAPTER 13 SERIAL ARRAY UNIT 13.3.11 Serial output enable register m (SOEm) The SOEm register is a register that is used to enable or stop output of the serial communication operation of each channel. Channel n that enables serial output cannot rewrite by software the value of the SOmn bit of serial output register m (SOm) to be described below, and a value reflected by a communication operation is output from the serial data output pin.
Page 413 RL78/G1D CHAPTER 13 SERIAL ARRAY UNIT 13.3.12 Serial output register m (SOm) The SOm register is a buffer register for serial output of each channel. The value of the SOmn bit of this register is output from the serial data output pin of channel n. The value of the CKOmn bit of this register is output from the serial clock output pin of channel n.
Page 414 RL78/G1D CHAPTER 13 SERIAL ARRAY UNIT 13.3.13 Serial output level register m (SOLm) The SOLm register is a register that is used to set inversion of the data output level of each channel. This register can be set only in the UART mode. Be sure to set 0 for corresponding bit in the CSI mode and simplifies C mode.
Page 415 RL78/G1D CHAPTER 13 SERIAL ARRAY UNIT 13.3.14 Serial standby control register 0 (SSC0) The SSC0 register is used to control the startup of reception (the SNOOZE mode) while in the STOP mode when receiving CSI00 or UART0 serial data. The SSC0 register can be set by a 16-bit memory manipulation instruction. The lower 8 bits of the SSC0 register can be set with an 8-bit memory manipulation instruction with SSC0L.
Page 416 RL78/G1D CHAPTER 13 SERIAL ARRAY UNIT 13.3.15 Noise filter enable register 0 (NFEN0) The NFEN0 register is used to set whether the noise filter can be used for the input signal from the serial data input pin to each channel. Disable the noise filter of the pin used for CSI or simplified I C communication, by clearing the corresponding bit of this register to 0.
Page 417 RL78/G1D CHAPTER 13 SERIAL ARRAY UNIT 13.3.16 Registers controlling port functions of serial input/output pins Using the serial array unit requires setting of the registers that control the port functions multiplexed on the target channel (port mode register (PMxx), port register (Pxx), port input mode register (PIMxx), port output mode register (POMxx), port mode control register (PMCxx)).
Page 418 RL78/G1D CHAPTER 13 SERIAL ARRAY UNIT 13.4 Operation stop mode Each serial interface of serial array unit has the operation stop mode. In this mode, serial communication cannot be executed, thus reducing the power consumption. In addition, the pin for serial interface can be used as port function pins in this mode. 13.4.1 Stopping the operation by units The stopping of the operation by units is set by using peripheral enable register 0 (PER0).
Page 419 RL78/G1D CHAPTER 13 SERIAL ARRAY UNIT 13.4.2 Stopping the operation by channels The stopping of the operation by channels is set using each of the following registers. Figure 13-23. Each Register Setting When Stopping the Operation by Channels (a) Serial channel stop register m (STm) … This register is a trigger register that is used to enable stopping communication/count by each channel.
Page 420 RL78/G1D CHAPTER 13 SERIAL ARRAY UNIT 13.5 Operation of 3-Wire Serial I/O (CSI00, CSI20, CSI21) Communication This is a clocked communication function that uses three lines: serial clock (SCK) and serial data (SI and SO) lines. [Data transmission/reception] ● Data length of 7 or 8 bits ●...
Page 421 RL78/G1D CHAPTER 13 SERIAL ARRAY UNIT The channels supporting 3-wire serial I/O (CSI00, CSI20, CSI21) are channels 0 and 2 of SAU0 and channel 1 of SAU1. Used as Simplified I Unit Channel Used as CSI Used as UART CSI00 UART0 IIC00 –...
Page 422 RL78/G1D CHAPTER 13 SERIAL ARRAY UNIT 13.5.1 Master transmission Master transmission is that the RL78 microcontroller outputs a transfer clock and transmits data to another device. 3-Wire Serial I/O CSI00 CSI20 CSI21 Target channel Channel 0 of SAU0 Channel 0 of SAU1 Channel 1 of SAU1 Pins used SCK00, SO00...
Page 423 RL78/G1D CHAPTER 13 SERIAL ARRAY UNIT (1) Register setting Figure 13-24. Example of Contents of Registers for Master Transmission of 3-Wire Serial I/O (CSI00, CSI20, CSI21) (1/2) (a) Serial mode register mn (SMRmn) SMRmn CKSmn CCSmn STSmn SISmn0 MDmn2 MDmn1 MDmn0 Operation clock (f ) of channel n...
Page 424 RL78/G1D CHAPTER 13 SERIAL ARRAY UNIT Figure 13-24. Example of Contents of Registers for Master Transmission of 3-Wire Serial I/O (CSI00, CSI20, CSI21) (2/2) (e) Serial output enable register m (SOEm) … Sets only the bits of the target channel to 1. SOEm SOEm3 SOEm2...
Page 425 RL78/G1D CHAPTER 13 SERIAL ARRAY UNIT (2) Operation procedure Figure 13-25. Initial Setting Procedure for Master Transmission Starting initial setting Release the serial array unit from the Setting the PER0 register reset status and start clock supply. Setting the SPSm register Set the operation clock.
Page 426 RL78/G1D CHAPTER 13 SERIAL ARRAY UNIT Figure 13-26. Procedure for Stopping Master Transmission Starting setting to stop If there is any data being transferred, wait for their completion. (Selective) TSFmn = 0? (If there is an urgent must stop, do not wait) Write 1 to the STmn bit of the target channel.
Page 427 RL78/G1D CHAPTER 13 SERIAL ARRAY UNIT Figure 13-27. Procedure for Resuming Master Transmission Starting setting for resumption Wait until stop the communication target (slave) or communication operation (Essential) Slave ready? completed Disable data output and clock output of Port manipulation (Essential) the target channel by setting a port register and a port mode register.
Page 428 RL78/G1D CHAPTER 13 SERIAL ARRAY UNIT (3) Processing flow (in single-transmission mode) Figure 13-28. Timing Chart of Master Transmission (in Single-Transmission Mode) (Type 1: DAPmn = 0, CKPmn = 0) SSmn STmn SEmn SDRmn Transmit data 1 Transmit data 2 Transmit data 3 SCKp pin SOp pin...
Page 429 RL78/G1D CHAPTER 13 SERIAL ARRAY UNIT Figure 13-29. Flowchart of Master Transmission (in Single-Transmission Mode) Starting CSI communication For the initial setting, refer to Figure 13-24. SAU default setting (Select Transfer end interrupt) Set data for transmission and the number of data. Clear communication end flag (Storage area, Transmission data pointer, Number of communication data and Setting transmit data Communication end flag are optionally set on the internal RAM by the software)
Page 430 RL78/G1D CHAPTER 13 SERIAL ARRAY UNIT (4) Processing flow (in continuous transmission mode) Figure 13-30. Timing Chart of Master Transmission (in Continuous Transmission Mode) (Type 1: DAPmn = 0, CKPmn = 0) <1> SSmn STmn <6> SEmn SDRmn Transmit data 1 Transmit data 2 Transmit data 3 SCKp pin...
Page 431 RL78/G1D CHAPTER 13 SERIAL ARRAY UNIT Figure 13-31. Flowchart of Master Transmission (in Continuous Transmission Mode) Starting setting For the initial setting, refer to Figure 13-24. <1> SAU default setting (Select buffer empty interrupt) Set data for transmission and the number of data. Clear communication end flag Setting transmit data (Storage area, Transmission data pointer, Number of communication data and Communication end flag are optionally set on the internal RAM by the software)
Page 432 RL78/G1D CHAPTER 13 SERIAL ARRAY UNIT 13.5.2 Master reception Master reception is that the RL78 microcontroller outputs a transfer clock and receives data from other device. 3-Wire Serial I/O CSI00 CSI20 CSI21 Target channel Channel 0 of SAU0 Channel 0 of SAU1 Channel 1 of SAU1 Pins used SCK00, SI00...
Page 433 RL78/G1D CHAPTER 13 SERIAL ARRAY UNIT (1) Register setting Figure 13-32. Example of Contents of Registers for Master Reception of 3-Wire Serial I/O (CSI00, CSI20) (1/2) (a) Serial mode register mn (SMRmn) SMRmn CKSmn CCSmn STSmn SISmn0 MDmn2 MDmn1 MDmn0 Operation clock (f ) of channel n Interrupt source of channel n...
Page 434 RL78/G1D CHAPTER 13 SERIAL ARRAY UNIT Figure 13-32. Example of Contents of Registers for Master Reception of 3-Wire Serial I/O (CSI00, CSI20) (2/2) (e) Serial output enable register m (SOEm) …The register that not used in this mode. SOEm SOEm3 SOEm2 SOEm1 SOEm0...
Page 435 RL78/G1D CHAPTER 13 SERIAL ARRAY UNIT (2) Operation procedure Figure 13-33. Initial Setting Procedure for Master Reception Starting initial setting Release the serial array unit from the Setting the PER0 register reset status and start clock supply. Setting the SPSm register Set the operation clock.
Page 436 RL78/G1D CHAPTER 13 SERIAL ARRAY UNIT Figure 13-35. Procedure for Resuming Master Reception Starting setting for resumption Wait until stop the communication target (slave) or communication operation Completing slave (Essential) completed preparations? Disable clock output of the target channel by setting a port register and a Port manipulation (Essential) port mode register.
Page 437 RL78/G1D CHAPTER 13 SERIAL ARRAY UNIT (3) Processing flow (in single-reception mode) Figure 13-36. Timing Chart of Master Reception (in Single-Reception Mode) (Type 1: DAPmn = 0, CKPmn = 0) SSmn STmn SEmn Receive data 2 Receive data 3 Receive data 1 SDRmn Dummy data for reception Dummy data...
Page 438 RL78/G1D CHAPTER 13 SERIAL ARRAY UNIT Figure 13-37. Flowchart of Master Reception (in Single-Reception Mode) Starting CSI communication For the initial setting, refer to Figure 13-32. SAU default setting (Select Transfer end interrupt) Setting storage area of the receive data, number of communication data (Storage area, Reception data pointer, Number of communication data and Setting receive data Communication end flag are optionally set on the internal RAM by the software)
Page 439 RL78/G1D CHAPTER 13 SERIAL ARRAY UNIT (4) Processing flow (in continuous reception mode) Figure 13-38. Timing Chart of Master Reception (in Continuous Reception Mode) (Type 1: DAPmn = 0, CKPmn = 0) <1> SSmn <8> STmn SEmn Receive data 3 SDRmn Dummy data Dummy data...
Page 440 RL78/G1D CHAPTER 13 SERIAL ARRAY UNIT Figure 13-39. Flowchart of Master Reception (in Continuous Reception Mode) Starting CSI communication For the initial setting, refer to Figure 13-32. buffer empty (Select interrupt) SAU default setting <1> Setting storage area of the receive data, number of communication data Setting receive data (Storage area, Reception data pointer, Number of communication data and Communication end flag are optionally set on the internal RAM by the software)
Page 441 RL78/G1D CHAPTER 13 SERIAL ARRAY UNIT 13.5.3 Master transmission/reception Master transmission/reception is that the RL78 microcontroller outputs a transfer clock and transmits/receives data to/from other device. 3-Wire Serial I/O CSI00 CSI20 CSI21 Target channel Channel 0 of SAU0 Channel 0 of SAU1 Channel 1 of SAU1 Pins used SCK00, SI00, SO00...
Page 442 RL78/G1D CHAPTER 13 SERIAL ARRAY UNIT (1) Register setting Figure 13-40. Example of Contents of Registers for Master Transmission/Reception of 3-Wire Serial I/O (CSI00, CSI20, CSI21) (1/2) (a) Serial mode register mn (SMRmn) SMRmn CKSmn CCSmn STSmn SISmn0 MDmn2 MDmn1 MDmn0 Operation clock (f ) of channel n...
Page 443 RL78/G1D CHAPTER 13 SERIAL ARRAY UNIT Figure 13-40. Example of Contents of Registers for Master Transmission/Reception of 3-Wire Serial I/O (CSI00, CSI20, CSI21) (2/2) (e) Serial output enable register m (SOEm) … Sets only the bits of the target channel to 1. SOEm SOEm3 SOEm2...
Page 444 RL78/G1D CHAPTER 13 SERIAL ARRAY UNIT (2) Operation procedure Figure 13-41. Initial Setting Procedure for Master Transmission/Reception Starting initial setting Release the serial array unit from the Setting the PER0 register reset status and start clock supply. Set the operation clock. Setting the SPSm register Set an operation mode, etc.
Page 445 RL78/G1D CHAPTER 13 SERIAL ARRAY UNIT Figure 13-42. Procedure for Stopping Master Transmission/Reception Starting setting to stop If there is any data being transferred, wait for their completion. (Selective) TSFmn = 0? (If there is an urgent must stop, do not wait) (Essential) Write 1 to the STmn bit of the target channel.
Page 446 RL78/G1D CHAPTER 13 SERIAL ARRAY UNIT Figure 13-43. Procedure for Resuming Master Transmission/Reception Starting setting for resumption Wait until stop the communication target (slave) or communication operation Completing slave (Essential) completed preparations? Disable data output and clock output of (Essential) the target channel by setting a port Port manipulation register and a port mode register.
Page 447 RL78/G1D CHAPTER 13 SERIAL ARRAY UNIT (3) Processing flow (in single-transmission/reception mode) Figure 13-44. Timing Chart of Master Transmission/Reception (in Single-Transmission/Reception Mode) (Type 1: DAPmn = 0, CKPmn = 0) SSmn STmn SEmn Receive data 3 Receive data 2 Receive data 1 SDRmn Transmit data 1 Transmit data 2...
Page 448 RL78/G1D CHAPTER 13 SERIAL ARRAY UNIT Figure 13-45. Flowchart of Master Transmission/Reception (in Single- Transmission/Reception Mode) Starting CSI communication For the initial setting, refer to Figure 13-40. SAU default setting (Select transfer end interrupt) Setting storage data and number of data for transmission/reception data Setting (Storage area, Transmission data pointer, Reception data pointer, Number of transmission/reception data...
Page 449 RL78/G1D CHAPTER 13 SERIAL ARRAY UNIT (4) Processing flow (in continuous transmission/reception mode) Figure 13-46. Timing Chart of Master Transmission/Reception (in Continuous Transmission/Reception Mode) (Type 1: DAPmn = 0, CKPmn = 0) <1> SSmn <8> STmn SEmn Receive data 3 SDRmn Transmit data 1 Transmit data 2...
Page 450 RL78/G1D CHAPTER 13 SERIAL ARRAY UNIT Figure 13-47. Flowchart of Master Transmission/Reception (in Continuous Transmission/Reception Mode) Starting setting For the initial setting, refer to Figure 13-40. <1> SAU default setting (Select buffer empty interrupt) Setting storage data and number of data for transmission/reception data Setting (Storage area, Transmission data pointer, Reception data, Number of transmission/reception data...
Page 451 RL78/G1D CHAPTER 13 SERIAL ARRAY UNIT 13.5.4 Slave transmission Slave transmission is that the RL78 microcontroller transmits data to another device in the state of a transfer clock being input from another device. 3-Wire Serial I/O CSI00 CSI20 CSI21 Target channel Channel 0 of SAU0 Channel 0 of SAU1 Channel 1 of SAU1...
Page 452 RL78/G1D CHAPTER 13 SERIAL ARRAY UNIT (1) Register setting Figure 13-48. Example of Contents of Registers for Slave Transmission of 3-Wire Serial I/O (CSI00, CSI20) (1/2) (a) Serial mode register mn (SMRmn) SMRmn CKSmn CCSmn STSmn SISmn0 MDmn2 MDmn1 MDmn0 Operation clock (f ) of channel n Interrupt source of channel n...
Page 453 RL78/G1D CHAPTER 13 SERIAL ARRAY UNIT Figure 13-48. Example of Contents of Registers for Slave Transmission of 3-Wire Serial I/O (CSI00, CSI20) (2/2) (e) Serial output enable register m (SOEm) … Sets only the bits of the target channel to 1. SOEm SOEm3 SOEm2...
Page 454 RL78/G1D CHAPTER 13 SERIAL ARRAY UNIT (2) Operation procedure Figure 13-49. Initial Setting Procedure for Slave Transmission Starting initial setting Release the serial array unit from the Setting the PER0 register reset status and start clock supply. Set the operation clock. Setting the SPSm register Set an operation mode, etc.
Page 455 RL78/G1D CHAPTER 13 SERIAL ARRAY UNIT Figure 13-50. Procedure for Stopping Slave Transmission Starting setting to stop If there is any data being transferred, wait for their completion. (Selective) TSFmn = 0? (If there is an urgent must stop, do not wait) (Essential) Write 1 to the STmn bit of the target channel.
Page 456 RL78/G1D CHAPTER 13 SERIAL ARRAY UNIT Figure 13-51. Procedure for Resuming Slave Transmission Starting setting for resumption Wait until stop the communication target Completing master (Essential) preparations? (master) Disable data output of the target channel by setting a port register and a port Port manipulation (Selective) mode register.
Page 457 RL78/G1D CHAPTER 13 SERIAL ARRAY UNIT Remark If PER0 is rewritten while stopping the master transmission and the clock supply is stopped, wait transmission until the target (master) stops or transmission finishes, and then perform initialization instead of restarting the transmission. R01UH0515EJ0120 Rev.1.20 Dec 16, 2016...
Page 458 RL78/G1D CHAPTER 13 SERIAL ARRAY UNIT (3) Processing flow (in single-transmission mode) Figure 13-52. Timing Chart of Slave Transmission (in Single-Transmission Mode) (Type 1: DAPmn = 0, CKPmn = 0) SSmn STmn SEmn SDRmn Transmit data 1 Transmit data 2 Transmit data 3 SCKp pin SOp pin...
Page 459 RL78/G1D CHAPTER 13 SERIAL ARRAY UNIT Figure 13-53. Flowchart of Slave Transmission (in Single-Transmission Mode) Starting CSI communication For the initial setting, refer to Figure 13-48. SAU default setting (Select transfer end interrupt) Set storage area and the number of data for transmit data Setting transmit data (Storage area, Transmission data pointer, Number of communication data and Communication end flag are optionally set on the internal RAM by the software)
Page 460 RL78/G1D CHAPTER 13 SERIAL ARRAY UNIT (4) Processing flow (in continuous transmission mode) Figure 13-54. Timing Chart of Slave Transmission (in Continuous Transmission Mode) (Type 1: DAPmn = 0, CKPmn = 0) <1> SSmn STmn <6> SEmn SDRmn Transmit data 1 Transmit data 2 Transmit data 3 SCKp pin...
Page 461 RL78/G1D CHAPTER 13 SERIAL ARRAY UNIT Figure 13-55. Flowchart of Slave Transmission (in Continuous Transmission Mode) Starting setting For the initial setting, refer to Figure 13-48. <1> SAU default setting (Select buffer empty interrupt) Setting transmit data Set storage area and the number of data for transmit data (Storage area, Transmission data pointer, Number of communication data and Communication end flag are optionally set on the internal RAM by the software) Clear interrupt request flag (XXIF), reset interrupt mask (XXMK) and set...
Page 462 RL78/G1D CHAPTER 13 SERIAL ARRAY UNIT 13.5.5 Slave reception Slave reception is that the RL78 microcontroller receives data from another device in the state of a transfer clock being input from another device. 3-Wire Serial I/O CSI00 CSI20 CSI21 Target channel Channel 0 of SAU0 Channel 0 of SAU1 Channel 1 of SAU1...
Page 463 RL78/G1D CHAPTER 13 SERIAL ARRAY UNIT (1) Register setting Figure 13-56. Example of Contents of Registers for Slave Reception of 3-Wire Serial I/O (CSI00, CSI20) (1/2) (a) Serial mode register mn (SMRmn) SMRmn CKSmn CCSmn STSmn SISmn0 MDmn2 MDmn1 MDmn0 Operation clock (f ) of channel n Interrupt source of channel n...
Page 464 RL78/G1D CHAPTER 13 SERIAL ARRAY UNIT Figure 13-56. Example of Contents of Registers for Slave Reception of 3-Wire Serial I/O (CSI00, CSI20) (2/2) (e) Serial output enable register m (SOEm) …The Register that not used in this mode. SOEm SOEm2 SOEm1 SOEm0 ×...
Page 465 RL78/G1D CHAPTER 13 SERIAL ARRAY UNIT (2) Operation procedure Figure 13-57. Initial Setting Procedure for Slave Reception Starting initial settings Release the serial array unit from the Setting the PER0 register reset status and start clock supply. Set the operation clock. Setting the SPSm register Set an operation mode, etc.
Page 466 RL78/G1D CHAPTER 13 SERIAL ARRAY UNIT Figure 13-59. Procedure for Resuming Slave Reception Starting setting for resumption Wait until stop the communication target (master) Completing master (Essential) preparations? Disable clock output of the target channel by setting a port register and a Port manipulation (Essential) port mode register.
Page 467 RL78/G1D CHAPTER 13 SERIAL ARRAY UNIT (3) Processing flow (in single-reception mode) Figure 13-60. Timing Chart of Slave Reception (in Single-Reception Mode) (Type 1: DAPmn = 0, CKPmn = 0) SSmn STmn SEmn Receive data 3 SDRmn Receive data 1 Receive data 2 Read Read...
Page 468 RL78/G1D CHAPTER 13 SERIAL ARRAY UNIT Figure 13-61. Flowchart of Slave Reception (in Single-Reception Mode) Starting CSI communication For the initial setting, refer to Figure 13-57. SAU default setting (Select transfer end interrupt only) Clear storage area setting and the number of receive data Ready for reception (Storage area, Reception data pointer, Number of communication data and Communication end flag are optionally set on the internal RAM by the software)
Page 469 RL78/G1D CHAPTER 13 SERIAL ARRAY UNIT 13.5.6 Slave transmission/reception Slave transmission/reception is that the RL78 microcontroller transmits/receives data to/from another device in the state of a transfer clock being input from another device. 3-Wire Serial I/O CSI00 CSI20 CSI21 Target channel Channel 0 of SAU0 Channel 0 of SAU1 Channel 1 of SAU1...
Page 470 RL78/G1D CHAPTER 13 SERIAL ARRAY UNIT (1) Register setting Figure 13-62. Example of Contents of Registers for Slave Transmission/Reception of 3-Wire Serial I/O (CSI00, CSI20) (1/2) (a) Serial mode register mn (SMRmn) SMRmn CKSmn CCSmn STSmn SISmn0 MDmn2 MDmn1 MDmn0 Operation clock (f ) of channel n Interrupt source of channel n...
Page 471 RL78/G1D CHAPTER 13 SERIAL ARRAY UNIT Figure 13-62. Example of Contents of Registers for Slave Transmission/Reception of 3-Wire Serial I/O (CSI00, CSI20) (2/2) (e) Serial output enable register m (SOEm) … Sets only the bits of the target channel to 1. SOEm SOEm2 SOEm1...
Page 472 RL78/G1D CHAPTER 13 SERIAL ARRAY UNIT (2) Operation procedure Figure 13-63. Initial Setting Procedure for Slave Transmission/Reception Starting initial setting Release the serial array unit from the Setting the PER0 register reset status and start clock supply. Set the operation clock. Setting the SPSm register Set an operation mode, etc.
Page 473 RL78/G1D CHAPTER 13 SERIAL ARRAY UNIT Figure 13-64. Procedure for Stopping Slave Transmission/Reception Starting setting to stop If there is any data being transferred, wait for their completion. (Selective) TSFmn = 0? (If there is an urgent must stop, do not wait) (Essential) Write 1 to the STmn bit of the target channel.
Page 474 RL78/G1D CHAPTER 13 SERIAL ARRAY UNIT Figure 13-65. Procedure for Resuming Slave Transmission/Reception Starting setting for resumption Wait until stop the communication target Completing master (Essential) (master) preparations? Disable data output of the target channel by setting a port register and a port (Essential) Port manipulation mode register.
Page 475 RL78/G1D CHAPTER 13 SERIAL ARRAY UNIT (3) Processing flow (in single-transmission/reception mode) Figure 13-66. Timing Chart of Slave Transmission/Reception (in Single-Transmission/Reception Mode) (Type 1: DAPmn = 0, CKPmn = 0) SSmn STmn SEmn Receive data 1 Receive data 2 Receive data 3 SDRmn Transmit data 1 Transmit data 2...
Page 476 RL78/G1D CHAPTER 13 SERIAL ARRAY UNIT Figure 13-67. Flowchart of Slave Transmission/Reception (in Single- Transmission/Reception Mode) Starting CSI communication For the initial setting, refer to Figure 13-63 SAU default setting (Select Transfer end interrupt) Setting storage area and number of data for transmission/reception data Setting (Storage area, Transmission/reception data pointer, Number of communication data transmission/reception data...
Page 477 RL78/G1D CHAPTER 13 SERIAL ARRAY UNIT (4) Processing flow (in continuous transmission/reception mode) Figure 13-68. Timing Chart of Slave Transmission/Reception (in Continuous Transmission/Reception Mode) (Type 1: DAPmn = 0, CKPmn = 0) <1> SSmn <8> STmn SEmn Receive data 3 SDRmn Transmit data 1 Transmit data 2...
Page 478 RL78/G1D CHAPTER 13 SERIAL ARRAY UNIT Figure 13-69. Flowchart of Slave Transmission/Reception (in Continuous Transmission/Reception Mode) Starting setting For the initial setting, refer to Figure 13-62 <1> SAU default setting (Select buffer empty interrupt) Setting storage area and number of data for transmission/reception data Setting (Storage area, Transmission/reception data pointer, Number of communication data and Communication end flag are optionally set on the internal RAM by the software)
Page 479 RL78/G1D CHAPTER 13 SERIAL ARRAY UNIT 13.5.7 SNOOZE mode function SNOOZE mode makes CSI operate reception by SCKp pin input detection while the STOP mode. Normally CSI stops communication in the STOP mode. But, using the SNOOZE mode makes reception CSI operate unless the CPU operation by detecting SCKp pin input.
Page 480 RL78/G1D CHAPTER 13 SERIAL ARRAY UNIT (1) SNOOZE mode operation (once startup) Figure 13-70. Timing Chart of SNOOZE Mode Operation (once startup) (Type 1: DAPmn = 0, CKPmn = 0) CPU operation status Normal operation STOP mode SNOOZE mode Normal operation <4>...
Page 481 RL78/G1D CHAPTER 13 SERIAL ARRAY UNIT Figure 13-71. Flowchart of SNOOZE Mode Operation (once startup) SNOOZE mode operation TSFmn = 0 for all channels? Become the operation STOP status (SEm0 = 0) <1> Write 1 to STm0 bit SMRm0, SCRm0: Communication setting SAU default setting SDRm0 [15:9]:...
Page 482 RL78/G1D CHAPTER 13 SERIAL ARRAY UNIT (2) SNOOZE mode operation (continuous startup) Figure 13-72. Timing Chart of SNOOZE Mode Operation (continuous startup) (Type 1: DAPmn = 0, CKPmn = 0) CPU operation status Normal operation STOP mode SNOOZE mode Normal operation STOP mode SNOOZE mode <4>...
Page 483 RL78/G1D CHAPTER 13 SERIAL ARRAY UNIT Figure 13-73. Flowchart of SNOOZE Mode Operation (continuous startup) SNOOZE mode operation TSFmn = 0 for all channels? Become the operation STOP status (SEm0 = 0) Write 1 to STm0 bit <1> SMRm0, SCRm0: Communication setting SAU default setting SDRm0[15:9]:...
Page 484 RL78/G1D CHAPTER 13 SERIAL ARRAY UNIT 13.5.8 Calculating transfer clock frequency The transfer clock frequency for 3-wire serial I/O (CSI00, CSI20, CSI21) communication can be calculated by the following expressions. (1) Master ÷ (Transfer clock frequency) = {Operation clock (f ) frequency of target channel} ÷...
Page 485 RL78/G1D CHAPTER 13 SERIAL ARRAY UNIT Table 13-2. Selection of Operation Clock For 3-Wire Serial I/O Note SMRmn SPSm Register Operation Clock (f Register CKSmn = 32 MHz 32 MHz 16 MHz 8 MHz 4 MHz 2 MHz 1 MHz 500 kHz 250 kHz 125 kHz...
Page 486 RL78/G1D CHAPTER 13 SERIAL ARRAY UNIT 13.5.9 Procedure for processing errors that occurred during 3-wire serial I/O (CSI00, CSI20, CSI21) communication The procedure for processing errors that occurred during 3-wire serial I/O (CSI00, CSI20, CSI21) communication is described in Figure 13-74. Figure 13-74.
Page 487 RL78/G1D CHAPTER 13 SERIAL ARRAY UNIT 13.6 Operation of UART (UART0, UART1) Communication This is a start-stop synchronization function using two lines: serial/data transmission (T D) and serial/data reception D) lines. By using these two communication lines, each data frame, which consist of a start bit, data, parity bit, and stop bit, is transferred asynchronously (using the internal baud rate) between the microcontroller and the other communication party.
Page 488 RL78/G1D CHAPTER 13 SERIAL ARRAY UNIT Select any function for each channel. Only the selected function is possible. If UART0 is selected for channels 0 and 1 of unit 0, for example, these channels cannot be used for CSI00. At this time, however, channel 2, 3, or other channels of the same unit can be used for a function other than UART0, such as UART1.
Page 489 RL78/G1D CHAPTER 13 SERIAL ARRAY UNIT 13.6.1 UART transmission UART transmission is an operation to transmit data from the RL78 microcontroller to another device asynchronously (start-stop synchronization). Of two channels used for UART, the even channel is used for UART transmission. UART UART0 UART1...
Page 490 RL78/G1D CHAPTER 13 SERIAL ARRAY UNIT (1) Register setting Figure 13-75. Example of Contents of Registers for UART Transmission of UART (UART0, UART1) (1/2) (a) Serial mode register mn (SMRmn) SMRmn CKSmn CCSmn MDmn2 MDmn1 MDmn0 Operation clock (f ) of channel n Interrupt source of channel n 0: Prescaler output clock CKm0 set by the SPSm register 0: Transfer end interrupt...
Page 491 RL78/G1D CHAPTER 13 SERIAL ARRAY UNIT Figure 13-75. Example of Contents of Registers for UART Transmission of UART (UART0, UART1) (2/2) (e) Serial output register m (SOm) … Sets only the bits of the target channel. CKOm2 CKOm1 CKOm0 SOm2 SOm1 SOm0 ×...
Page 492 RL78/G1D CHAPTER 13 SERIAL ARRAY UNIT (2) Operation procedure Figure 13-76. Initial Setting Procedure for UART Transmission Starting initial setting Release the serial array unit from the Setting the PER0 register reset status and start clock supply. Set the operation clock. Setting the SPSm register Set an operation mode, etc.
Page 493 RL78/G1D CHAPTER 13 SERIAL ARRAY UNIT Figure 13-77. Procedure for Stopping UART Transmission Starting setting to stop If there is any data being transferred, wait for their completion. (Selective) TSFmn = 0? (If there is an urgent must stop, do not wait) (Essential) Write 1 to the STmn bit of the target channel.
Page 494 RL78/G1D CHAPTER 13 SERIAL ARRAY UNIT Figure 13-78. Procedure for Resuming UART Transmission Starting setting for resumption Wait until stop the communication target Completing master (Essential) preparations? or communication operation completed Disable data output of the target channel (Selective) Port manipulation by setting a port register and a port mode register.
Page 495 RL78/G1D CHAPTER 13 SERIAL ARRAY UNIT (3) Processing flow (in single-transmission mode) Figure 13-79. Timing Chart of UART Transmission (in Single-Transmission Mode) SSmn STmn SEmn SDRmn Transmit data 1 Transmit data 2 Transmit data 3 TxDq pin Transmit data 1 Transmit data 2 Transmit data 3 P SP...
Page 496 RL78/G1D CHAPTER 13 SERIAL ARRAY UNIT Figure 13-80. Flowchart of UART Transmission (in Single-Transmission Mode) Starting UART communication For the initial setting, refer to Figure 13-75. SAU default setting (Select transfer end interrupt) Set data for transmission and the number of data. Clear communication end flag (Storage area, transmission data pointer, number of communication data and Setting transmit data communication end flag are optionally set on the internal RAM by the software)
Page 497 RL78/G1D CHAPTER 13 SERIAL ARRAY UNIT (4) Processing flow (in continuous transmission mode) Figure 13-81. Timing Chart of UART Transmission (in Continuous Transmission Mode) <1> SSmn <6> STmn SEmn SDRmn Transmit data 1 Transmit data 2 Transmit data 3 TxDq pin P SP Transmit data 2 Transmit data 1...
Page 498 RL78/G1D CHAPTER 13 SERIAL ARRAY UNIT Figure 13-82. Flowchart of UART Transmission (in Continuous Transmission Mode) Starting UART communication For the initial setting, refer to Figure 13-75. <1> SAU default setting (Select buffer empty interrupt) Set data for transmission and the number of data. Clear communication end flag Setting transmit data (Storage area, Transmission data pointer, Number of communication data and Communication end flag are optionally set on the internal RAM by the software)
Page 499 RL78/G1D CHAPTER 13 SERIAL ARRAY UNIT 13.6.2 UART reception UART reception is an operation wherein the RL78 microcontroller asynchronously receives data from another device (start-stop synchronization). For UART reception, the odd-number channel of the two channels used for UART is used. The SMR register of both the odd- and even-numbered channels must be set.
Page 500 RL78/G1D CHAPTER 13 SERIAL ARRAY UNIT (1) Register setting Figure 13-83. Example of Contents of Registers for UART Reception of UART (UART0, UART1) (1/2) (a) Serial mode register mn (SMRmn) SMRmn CKSmn CCSmn STSmn SISmn0 MDmn2 MDmn1 MDmn0 Operation clock (f ) of channel n 0: Normal reception Operation mode of channel n...
Page 501 RL78/G1D CHAPTER 13 SERIAL ARRAY UNIT Figure 13-83. Example of Contents of Registers for UART Reception of UART (UART0, UART1) (2/2) (e) Serial output register m (SOm) … The register that not used in this mode. CKOm2 CKOm1 CKOm0 SOm2 SOm1 SOm0 ×...
Page 502 RL78/G1D CHAPTER 13 SERIAL ARRAY UNIT (2) Operation procedure Figure 13-84. Initial Setting Procedure for UART Reception Starting initial setting Release the serial array unit from the Setting the PER0 register reset status and start clock supply. Set the operation clock. Setting the SPSm register Set an operation mode, etc.
Page 503 RL78/G1D CHAPTER 13 SERIAL ARRAY UNIT Figure 13-86. Procedure for Resuming UART Reception Starting setting for resumption Stop the target for communication or wait Completing master until completes its communication (Essential) preparations? operation. Re-set the register to change the operation (Selective) Changing setting of the SPSm register clock setting.
Page 504 RL78/G1D CHAPTER 13 SERIAL ARRAY UNIT (3) Processing flow Figure 13-87. Timing Chart of UART Reception SSmn STmn SEmn Receive data 3 SDRmn Receive data 1 Receive data 2 RxDq pin Receive data 3 Receive data 2 Receive data 1 Shift Shift operation Shift operation...
Page 505 RL78/G1D CHAPTER 13 SERIAL ARRAY UNIT Figure 13-88. Flowchart of UART Reception Starting UART communication For the initial setting, refer to Figure 13-83. (setting to mask for error interrupt) SAU default setting Setting storage area of the receive data, number of communication Setting receive data data (storage area, reception data pointer, number of communication data and communication end flag are optionally set on the internal...
Page 506 RL78/G1D CHAPTER 13 SERIAL ARRAY UNIT 13.6.3 SNOOZE mode function The SNOOZE mode makes the UART perform reception operations upon RxDq pin input detection while in the STOP mode. Normally the UART stops communication in the STOP mode. However, using the SNOOZE mode enables the UART to perform reception operations without CPU operation.
Page 507 RL78/G1D CHAPTER 13 SERIAL ARRAY UNIT Table 13-3. Baud Rate Setting for UART Reception in SNOOZE Mode High-speed On-chip Baud Rate for UART Reception in SNOOZE Mode Oscillator (f Baud Rate of 4800 bps Operation Clock (f SDRmn[15:9] Maximum Minimum Permissible Permissible Value Value Note...
Page 508 RL78/G1D CHAPTER 13 SERIAL ARRAY UNIT (1) SNOOZE mode operation (EOCm1 = 0, SSECm = 0/1) Because of the setting of EOCm1 = 0, even though a communication error occurs, an error interrupt (INTSRE0) is not generated, regardless of the setting of the SSECm bit. A transfer end interrupt (INTSR0) will be generated. Figure 13-89.
Page 509 RL78/G1D CHAPTER 13 SERIAL ARRAY UNIT (2) SNOOZE mode operation (EOCm1 = 1, SSECm = 0: Error interrupt (INTSREq) generation is enabled) Because EOCm1 = 1 and SSECm = 0, an error interrupt (INTSREq) is generated when a communication error occurs.
Page 510 RL78/G1D CHAPTER 13 SERIAL ARRAY UNIT Figure 13-91. Flowchart of SNOOZE Mode Operation (EOCm1 = 0, SSECm = 0/1 or EOCm1 = 1, SSECm = 0) Setting start Does TSFmn = 0 on all channels? The operation of all channels is also stopped to switch to the Writing 1 to the STmn bit <1>...
Page 511 RL78/G1D CHAPTER 13 SERIAL ARRAY UNIT (3) SNOOZE mode operation (EOCm1 = 1, SSECm = 1: Error interrupt (INTSREq) generation is stopped) Because EOCm1 = 1 and SSECm = 1, an error interrupt (INTSREq) is not generated when a communication error occurs.
Page 512 RL78/G1D CHAPTER 13 SERIAL ARRAY UNIT Figure 13-93. Flowchart of SNOOZE Mode Operation (EOCm1 = 1, SSECm = 1) Setting start Does TSFmn = 0 on all channels? Clear the all error flags SIRm1 = 0007H The operation of all channels is also stopped to switch to Writing 1 to the STmn bit <1>...
Page 513 RL78/G1D CHAPTER 13 SERIAL ARRAY UNIT Caution If a parity error, framing error, or overrun error occurs while the SSECm bit is set to 1, the PEFm1, FEFm1, or OVFm1 flag is not set and an error interrupt (INTSREq) is not generated. Therefore, when the setting of SSECm = 1 is made, clear the PEFm1, FEFm1, or OVFm1 flag before setting the SWCm bit to 1 and read the value in SDRm1[7:0] (RxDq register) (8 bits) or SDRm1[8:0] (9 bits).
Page 514 RL78/G1D CHAPTER 13 SERIAL ARRAY UNIT 13.6.4 Calculating baud rate (1) Baud rate calculation expression The baud rate for UART (UART0 and UART1) communication can be calculated by the following expressions. (Baud rate) = {Operation clock (f ) frequency of target channel} ÷ (SDRmn[15:9] + 1) ÷ 2 [bps] Caution Setting serial data register mn (SDRmn) SDRmn[15:9] = (0000000B, 0000001B) is prohibited.
Page 515 RL78/G1D CHAPTER 13 SERIAL ARRAY UNIT Table 13-4. Selection of Operation Clock For UART Note SMRmn SPSm Register Operation Clock (f Register CKSmn = 32 MHz 32 MHz 16 MHz 8 MHz 4 MHz 2 MHz 1 MHz 500 kHz 250 kHz 125 kHz 62.5 kHz...
Page 516 RL78/G1D CHAPTER 13 SERIAL ARRAY UNIT (2) Baud rate error during transmission The baud rate error of UART (UART0 and UART1) communication during transmission can be calculated by the following expression. Make sure that the baud rate at the transmission side is within the permissible baud rate range at the reception side.
Page 517 RL78/G1D CHAPTER 13 SERIAL ARRAY UNIT (3) Permissible baud rate range for reception The permissible baud rate range for reception during UART (UART0 and UART1) communication can be calculated by the following expression. Make sure that the baud rate at the transmission side is within the permissible baud rate range at the reception side.
Page 518 RL78/G1D CHAPTER 13 SERIAL ARRAY UNIT 13.6.5 Procedure for processing errors that occurred during UART (UART0 and UART1) communication The procedure for processing errors that occurred during UART (UART0 and UART1) communication is described in Figures 13-94 and 13-95. Figure 13-95. Processing Procedure in Case of Parity Error or Overrun Error Software Manipulation Hardware Status Remark...
Page 519 RL78/G1D CHAPTER 13 SERIAL ARRAY UNIT 13.7 Operation of Simplified I C (IIC00, IIC20) Communication This is a clocked communication function to communicate with two or more devices by using two lines: serial clock (SCL) and serial data (SDA). This communication function is designed to execute single communication with devices such as EEPROM, flash memory, and A/D converter, and therefore, can be used only by the master.
Page 520 RL78/G1D CHAPTER 13 SERIAL ARRAY UNIT The channel supporting simplified I C (IIC00, IIC20) is channel 0 of SAU0 and SAU1. Used as Simplified I Unit Channel Used as CSI Used as UART CSI00 UART0 IIC00 – – UART1 – –...
Page 521 RL78/G1D CHAPTER 13 SERIAL ARRAY UNIT 13.7.1 Address field transmission Address field transmission is a transmission operation that first executes in I C communication to identify the target for transfer (slave). After a start condition is generated, an address (7 bits) and a transfer direction (1 bit) are transmitted in one frame.
Page 522 RL78/G1D CHAPTER 13 SERIAL ARRAY UNIT (1) Register setting Figure 13-97. Example of Contents of Registers for Address Field Transmission of Simplified I C (IIC00, IIC20) (a) Serial mode register mn (SMRmn) SMRmn CKSmn CCSmn STSmn SISmn0 MDmn2 MDmn1 MDmn0 Note 1 Note 1 Operation clock (f...
Page 523 RL78/G1D CHAPTER 13 SERIAL ARRAY UNIT Remarks 1. m: Unit number (m = 0, 1), n: Channel number (n = 0), r: IIC number (r = 00, 20), mn = 00, 10 : Setting is fixed in the IIC mode, : Setting disabled (set to the initial value) ×: Bit that cannot be used in this mode (set to the initial value when not used in any mode) 0/1: Set to 0 or 1 depending on the usage of the user...
Page 524 RL78/G1D CHAPTER 13 SERIAL ARRAY UNIT (2) Operation procedure Figure 13-98. Initial Setting Procedure for Simplified I Starting initial setting Release the serial array unit from the Setting the PER0 register reset status and start clock supply. Set the operation clock. Setting the SPSm register Set an operation mode, etc.
Page 525 RL78/G1D CHAPTER 13 SERIAL ARRAY UNIT (3) Processing flow Figure 13-99. Timing Chart of Address Field Transmission SSmn SEmn SOEmn SDRmn Address field transmission SCLr output CKOmn bit manipulation SDAr output SOmn bit manipulation Address SDAr input Shift Shift operation register mn INTIICr TSFmn...
Page 526 RL78/G1D CHAPTER 13 SERIAL ARRAY UNIT Figure 13-100. Flowchart of Simplified I C Address Field Transmission Tra nsmitt ing address field For the initial setting, refer to Figure 13-96 Default setting Writing 0 to the SOmn bit Set the SOmn bit to 0 Start condition generate Wait To secure a hold time of SCL signal...
Page 527 RL78/G1D CHAPTER 13 SERIAL ARRAY UNIT 13.7.2 Data transmission Data transmission is an operation to transmit data to the target for transfer (slave) after transmission of an address field. After all data are transmitted to the slave, a stop condition is generated and the bus is released. Simplified I IIC00 IIC20...
Page 528 RL78/G1D CHAPTER 13 SERIAL ARRAY UNIT (1) Register setting Figure 13-101. Example of Contents of Registers for Data Transmission of Simplified I C (IIC00, IIC20) (1/2) (a) Serial mode register mn (SMRmn) … Do not manipulate this register during data transmission/reception.
Page 529 RL78/G1D CHAPTER 13 SERIAL ARRAY UNIT Figure 13-101. Example of Contents of Registers for Data Transmission of Simplified I C (IIC00, IIC20) (2/2) (f) Serial channel start register m (SSm) … Do not manipulate this register during data transmission/reception. SSm3 SSm2 SSm1 SSm0...
Page 530 RL78/G1D CHAPTER 13 SERIAL ARRAY UNIT (2) Processing flow Figure 13-102. Timing Chart of Data Transmission SSmn “L” SEmn “H” SOEmn “H” SDRmn Transmit data 1 SCLr output SDAr output SDAr input Shift Shift operation register mn INTIICr TSFmn Figure 13-103. Flowchart of Simplified I C Data Transmission Address field transmission completed...
Page 531 RL78/G1D CHAPTER 13 SERIAL ARRAY UNIT 13.7.3 Data reception Data reception is an operation to receive data to the target for transfer (slave) after transmission of an address field. After all data are received to the slave, a stop condition is generated and the bus is released. Simplified I IIC00 IIC20...
Page 532 RL78/G1D CHAPTER 13 SERIAL ARRAY UNIT (1) Register setting Figure 13-104. Example of Contents of Registers for Data Reception of Simplified I C (IIC00, IIC20) (1/2) (a) Serial mode register mn (SMRmn) … Do not manipulate this register during data transmission/reception.
Page 533 RL78/G1D CHAPTER 13 SERIAL ARRAY UNIT ×: Bit that cannot be used in this mode (set to the initial value when not used in any mode) 0/1: Set to 0 or 1 depending on the usage of the user R01UH0515EJ0120 Rev.1.20 Dec 16, 2016...
Page 534 RL78/G1D CHAPTER 13 SERIAL ARRAY UNIT Figure 13-104. Example of Contents of Registers for Data Reception of Simplified I C (IIC00, IIC20) (2/2) (f) Serial channel start register m (SSm) … Do not manipulate this register during data transmission/reception. SSm3 SSm2 SSm1 SSm0...
Page 535 RL78/G1D CHAPTER 13 SERIAL ARRAY UNIT (2) Processing flow Figure 13-105. Timing Chart of Data Reception (a) When starting data reception SSmn STmn SEmn SOEmn “H” TXEmn, TXEmn = 1 / RXEmn = 0 TXEmn = 0 / RXEmn = 1 RXEmn SDRmn Dummy data (FFH)
Page 536 RL78/G1D CHAPTER 13 SERIAL ARRAY UNIT Figure 13-106. Flowchart of Data Reception Address field transmission completed Data reception completed Stop operation for rewriting SCRmn Writing 1 to the STmn bit register. Set to receive only the operating Writing 0 to the TXEmn bit, and 1 to the RXEmn bit mode of the channel.
Page 537 RL78/G1D CHAPTER 13 SERIAL ARRAY UNIT 13.7.4 Stop condition generation After all data are transmitted to or received from the target slave, a stop condition is generated and the bus is released. (1) Processing flow Figure 13-107. Timing Chart of Stop Condition Generation STmn SEmn SOEmn...
Page 538 RL78/G1D CHAPTER 13 SERIAL ARRAY UNIT 13.7.5 Calculating transfer rate The transfer rate for simplified I C (IIC00, IIC20) communication can be calculated by the following expressions. (Transfer rate) = {Operation clock (f ) frequency of target channel} ÷ (SDRmn[15:9] + 1) ÷ 2 Caution SDRmn[15:9] must not be set to 00000000B.
Page 539 RL78/G1D CHAPTER 13 SERIAL ARRAY UNIT Table 13-5. Selection of Operation Clock For Simplified I Note SMRmn SPSm Register Operation Clock (f Register CKSmn = 32 MHz 32 MHz 16 MHz 8 MHz 4 MHz 2 MHz 1 MHz 500 kHz 250 kHz 125 kHz 62.5 kHz...
Page 540 RL78/G1D CHAPTER 13 SERIAL ARRAY UNIT 13.7.6 Procedure for processing errors that occurred during simplified I C (IIC00, IIC20) communication The procedure for processing errors that occurred during simplified I C (IIC00, IIC20) communication is described in Figures 13-108 and 13-109. Figure 13-109.
Page 541 RL78/G1D CHAPTER 14 SERIAL INTERFACE IICA CHAPTER 14 SERIAL INTERFACE IICA 14.1 Functions of Serial Interface IICA Serial interface IICA has the following three modes. (1) Operation stop mode This mode is used when serial transfers are not performed. It can therefore be used to reduce power consumption. (2) I C bus mode (multimaster supported) This mode is used for 8-bit data transfers with several devices via two lines: a serial clock (SCLAn) line and a serial...
Page 542 RL78/G1D CHAPTER 14 SERIAL INTERFACE IICA Figure 14-1. Block Diagram of Serial Interface IICA0 Internal bus IICA status register 0 (IICS0) WUP0 MSTS0 ALD0 EXC0 COI0 TRC0 ACKD0 STD0 SPD0 IICA control register 00 (IICCTL00) Sub-circuit for standby IICE0 LREL0 WREL0 SPIE0 WTIM0 ACKE0 STT0 SPT0 Filter Start Slave address...
Page 543 RL78/G1D CHAPTER 14 SERIAL INTERFACE IICA Figure 14-2 shows a serial bus configuration example. Figure 14-2. Serial Bus Configuration Example Using I C Bus Serial data bus Master CPU1 Master CPU2 SDAAn SDAAn Slave CPU1 Slave CPU2 Serial clock SCLAn SCLAn Address 0 Address 1...
Page 544 RL78/G1D CHAPTER 14 SERIAL INTERFACE IICA 14.2 Configuration of Serial Interface IICA Serial interface IICA includes the following hardware. Table 14-1. Configuration of Serial Interface IICA Item Configuration Registers IICA shift register n (IICAn) Slave address register n (SVAn) Peripheral enable register 0 (PER0) Control registers IICA control register n0 (IICCTLn0) IICA status register n (IICSn)
Page 545 RL78/G1D CHAPTER 14 SERIAL INTERFACE IICA (2) Slave address register n (SVAn) This register stores seven bits of local addresses {A6, A5, A4, A3, A2, A1, A0} when in slave mode. The SVAn register can be set by an 8-bit memory manipulation instruction. However, rewriting to this register is prohibited while STDn = 1 (while the start condition is detected).
Page 546 RL78/G1D CHAPTER 14 SERIAL INTERFACE IICA (11) Start condition generator This circuit generates a start condition when the STTn bit is set to 1. However, in the communication reservation disabled status (IICRSVn bit = 1), when the bus is not released (IICBSYn bit = 1), start condition requests are ignored and the STCFn bit is set to 1.
Page 547 RL78/G1D CHAPTER 14 SERIAL INTERFACE IICA 14.3 Registers Controlling Serial Interface IICA Serial interface IICA is controlled by the following registers. ● Peripheral enable register 0 (PER0) ● IICA control register n0 (IICCTLn0) ● IICA flag register n (IICFn) ● IICA status register n (IICSn) ●...
Page 548 RL78/G1D CHAPTER 14 SERIAL INTERFACE IICA 14.3.1 Peripheral enable register 0 (PER0) This register is used to enable or disable supplying the clock to the peripheral hardware. Clock supply to a hardware macro that is not used is stopped in order to reduce the power consumption and noise. When serial interface IICAn is used, be sure to set bits 6, 4 (IICA1EN, IICA0EN) of this register to 1.
Page 549 RL78/G1D CHAPTER 14 SERIAL INTERFACE IICA Figure 14-6. Format of IICA Control Register n0 (IICCTLn0) (1/4) Address: F0230H (IICCTL00), F0238H (IICCTL10) After reset: 00H Symbol <7> <6> <5> <4> <3> <2> <1> <0> IICCTLn0 IICEn LRELn WRELn SPIEn WTIMn ACKEn STTn SPTn IICEn...
Page 550 RL78/G1D CHAPTER 14 SERIAL INTERFACE IICA Figure 14-6. Format of IICA Control Register n0 (IICCTLn0) (2/4) Note 1 SPIEn Enable/disable generation of interrupt request when stop condition is detected Disable Enable If the WUPn bit of IICA control register n1 (IICCTLn1) is 1, no stop condition interrupt will be generated even if SPIEn = 1.
Page 551 RL78/G1D CHAPTER 14 SERIAL INTERFACE IICA Figure 14-6. Format of IICA Control Register n0 (IICCTLn0) (3/4) Notes STTn Start condition trigger 1, 2 Do not generate a start condition. When bus is released (in standby state, when IICBSYn = 0): If this bit is set (1), a start condition is generated (startup as the master).
Page 552 RL78/G1D CHAPTER 14 SERIAL INTERFACE IICA Figure 14-6. Format of IICA Control Register n0 (IICCTLn0) (4/4) Note SPTn Stop condition trigger Stop condition is not generated. Stop condition is generated (termination of master device’s transfer). Cautions concerning set timing ● For master reception: Cannot be set to 1 during transfer.
Page 553 RL78/G1D CHAPTER 14 SERIAL INTERFACE IICA 14.3.3 IICA status register n (IICSn) This register indicates the status of I The IICSn register is read by a 1-bit or 8-bit memory manipulation instruction only when STTn = 1 and during the wait period.
Page 554 RL78/G1D CHAPTER 14 SERIAL INTERFACE IICA Figure 14-7. Format of IICA Status Register n (IICSn) (2/3) EXCn Detection of extension code reception Extension code was not received. Extension code was received. Condition for clearing (EXCn = 0) Condition for setting (EXCn = 1) ●...
Page 555 RL78/G1D CHAPTER 14 SERIAL INTERFACE IICA Figure 14-7. Format of IICA Status Register n (IICSn) (3/3) ACKDn Detection of acknowledge (ACK) Acknowledge was not detected. Acknowledge was detected. Condition for clearing (ACKDn = 0) Condition for setting (ACKDn = 1) ●...
Page 556 RL78/G1D CHAPTER 14 SERIAL INTERFACE IICA Figure 14-8. Format of IICA Flag Register n (IICFn) Note Address: FFF52H (IICF0), FFF56H (IICF1) After reset: 00H <7> <6> <1> <0> Symbol IICFn STCFn IICBSYn STCENn IICRSVn STCFn STTn clear flag Generate start condition Start condition generation unsuccessful: clear the STTn flag Condition for clearing (STCFn = 0) Condition for setting (STCFn = 1)
Page 557 RL78/G1D CHAPTER 14 SERIAL INTERFACE IICA 14.3.5 IICA control register n1 (IICCTLn1) This register is used to set the operation mode of I C and detect the statuses of the SCLAn and SDAAn pins. The IICCTLn1 register can be set by a 1-bit or 8-bit memory manipulation instruction. However, the CLDn and DADn bits are read-only.
Page 558 RL78/G1D CHAPTER 14 SERIAL INTERFACE IICA Figure 14-9. Format of IICA Control Register n1 (IICCTLn1) (2/2) CLDn Detection of SCLAn pin level (valid only when IICEn = 1) The SCLAn pin was detected at low level. The SCLAn pin was detected at high level. Condition for clearing (CLDn = 0) Condition for setting (CLDn = 1) ●...
Page 559 RL78/G1D CHAPTER 14 SERIAL INTERFACE IICA 14.3.6 IICA low-level width setting register n (IICWLn) This register is used to set the low-level width (t ) of the SCLAn pin signal that is output by serial interface IICA and to control the SDAAn pin signal. The IICWLn register can be set by an 8-bit memory manipulation instruction.
Page 560 RL78/G1D CHAPTER 14 SERIAL INTERFACE IICA 14.3.8 Port mode register 6 (PM6) This register sets the input/output of port 6 in 1-bit units. When using the P60/SCLA0 pin as clock I/O and the P61/SDAA0 pin as serial data I/O, clear PM60 and PM61, and the output latches of P60 and P61 to 0.
Page 561 RL78/G1D CHAPTER 14 SERIAL INTERFACE IICA 14.4 I C Bus Mode Functions 14.4.1 Pin configuration The serial clock pin (SCLAn) and the serial data bus pin (SDAAn) are configured as follows. (1) SCLAn ..This pin is used for serial clock input and output. This pin is an N-ch open-drain output for both master and slave devices.
Page 562 RL78/G1D CHAPTER 14 SERIAL INTERFACE IICA 14.4.2 Setting transfer clock by using IICWLn and IICWHn registers (1) Setting transfer clock on master side Transfer clock = IICWL + IICWH + f At this time, the optimal setting values of the IICWLn and IICWHn registers are as follows. (The fractional parts of all setting values are rounded up.) ●...
Page 563 RL78/G1D CHAPTER 14 SERIAL INTERFACE IICA Cautions1. The fastest operation frequency of the IICA operation clock (f ) is 20 MHz (max.). Set bit 0 (PRSn) of the IICA control register n1 (IICCTLn1) to "1" only when the f exceeds 20 MHz.
Page 564 RL78/G1D CHAPTER 14 SERIAL INTERFACE IICA 14.5 I C Bus Definitions and Control Methods The following section describes the I C bus’s serial data communication format and the signals used by the I C bus. Figure 14-14 shows the transfer timing for the “start condition”, “address”, “data”, and “stop condition” output via the I bus’s serial data bus.
Page 565 RL78/G1D CHAPTER 14 SERIAL INTERFACE IICA 14.5.2 Addresses The address is defined by the 7 bits of data that follow the start condition. An address is a 7-bit data segment that is output in order to select one of the slave devices that are connected to the master device via the bus lines.
Page 566 RL78/G1D CHAPTER 14 SERIAL INTERFACE IICA 14.5.4 Acknowledge (ACK) ACK is used to check the status of serial data at the transmission and reception sides. The reception side returns ACK each time it has received 8-bit data. The transmission side usually receives ACK after transmitting 8-bit data. When ACK is returned from the reception side, it is assumed that reception has been correctly performed and processing is continued.
Page 567 RL78/G1D CHAPTER 14 SERIAL INTERFACE IICA 14.5.5 Stop condition When the SCLAn pin is at high level, changing the SDAAn pin from low level to high level generates a stop condition. A stop condition is a signal that the master device generates to the slave device when serial transfer has been completed.
Page 568 RL78/G1D CHAPTER 14 SERIAL INTERFACE IICA 14.5.6 Wait The wait is used to notify the communication partner that a device (master or slave) is preparing to transmit or receive data (i.e., is in a wait state). Setting the SCLAn pin to low level notifies the communication partner of the wait state. When wait state has been canceled for both the master and slave devices, the next data transfer can begin.
Page 569 RL78/G1D CHAPTER 14 SERIAL INTERFACE IICA Figure 14-20. Wait (2/2) (b) When master and slave devices both have a nine-clock wait (master transmits, slave receives, and ACKEn = 1) Master Master and slave both wait after output of ninth clock IICAn data write (cancel wait) IICAn SCLAn...
Page 570 RL78/G1D CHAPTER 14 SERIAL INTERFACE IICA 14.5.7 Canceling wait The I C usually cancels a wait state by the following processing. ● Writing data to the IICA shift register n (IICAn) ● Setting bit 5 (WRELn) of IICA control register n0 (IICCTLn0) (canceling wait) Note ●...
Page 571 RL78/G1D CHAPTER 14 SERIAL INTERFACE IICA 14.5.8 Interrupt request (INTIICAn) generation timing and wait control The setting of bit 3 (WTIMn) of IICA control register n0 (IICCTLn0) determines the timing by which INTIICAn is generated and the corresponding wait control, as shown in Table 14-2. Table 14-2.
Page 572 RL78/G1D CHAPTER 14 SERIAL INTERFACE IICA 14.5.9 Address match detection method In I C bus mode, the master device can select a particular slave device by transmitting the corresponding slave address. Address match can be detected automatically by hardware. An interrupt request (INTIICAn) occurs when the address set to the slave address register n (SVAn) matches the slave address sent by the master device, or when an extension code has been received.
Page 573 RL78/G1D CHAPTER 14 SERIAL INTERFACE IICA 14.5.12 Arbitration When several master devices simultaneously generate a start condition (when the STTn bit is set to 1 before the STDn bit is set to 1), communication among the master devices is performed as the number of clocks are adjusted until the data differs.
Page 574 RL78/G1D CHAPTER 14 SERIAL INTERFACE IICA Table 14-4. Status During Arbitration and Interrupt Request Generation Timing Status During Arbitration Interrupt Request Generation Timing Note During address transmission At falling edge of eighth or ninth clock following byte transfer Read/write data after address transmission During extension code transmission Read/write data after extension code transmission During data transmission...
Page 575 RL78/G1D CHAPTER 14 SERIAL INTERFACE IICA 14.5.13 Wakeup function The I C bus slave function is a function that generates an interrupt request signal (INTIICAn) when a local address and extension code have been received. This function makes processing more efficient by preventing unnecessary INTIICAn signal from occurring when addresses do not match.
Page 576 RL78/G1D CHAPTER 14 SERIAL INTERFACE IICA Figure 14-23. Flow When Setting WUPn = 0 upon Address Match (Including Extension Code Reception) STOP mode state INTIICAn = 1? WUPn = 0 Wait Waits for five cycles of f Reading IICSn Executes processing corresponding to the operation to be executed after checking the operation state of serial interface IICA.
Page 577 RL78/G1D CHAPTER 14 SERIAL INTERFACE IICA Figure 14-24. When Operating as Master Device after Releasing STOP Mode other than by INTIICAn START SPIEn = 1 WUPn = 1 Waits for three cycles of f Wait STOP instruction STOP mode state Releasing STOP mode Releases STOP mode by an interrupt other than INTIICAn WUPn = 0...
Page 578 RL78/G1D CHAPTER 14 SERIAL INTERFACE IICA 14.5.14 Communication reservation (1) When communication reservation function is enabled (bit n (IICRSVn) of IICA flag register n (IICFn) = 0) To start master device communications when not currently using a bus, a communication reservation can be made to enable transmission of a start condition when the bus is released.
Page 579 RL78/G1D CHAPTER 14 SERIAL INTERFACE IICA Figure 14-25 shows the communication reservation timing. Figure 14-25. Communication Reservation Timing Write to Program processing STTn = 1 IICAn Communi- Set SPDn cation Hardware processing STDn reservation INTIICAn SCLAn SDAAn Generate by master device with bus mastership Remark IICAn: IICA shift register n...
Page 580 RL78/G1D CHAPTER 14 SERIAL INTERFACE IICA Figure 14-27. Communication Reservation Protocol SET1 STTn Sets STTn flag (communication reservation) Defines that communication reservation is in effect Define communication (defines and sets user flag to any part of RAM) reservation Note 1 Secures wait time by software.
Page 581 RL78/G1D CHAPTER 14 SERIAL INTERFACE IICA (2) When communication reservation function is disabled (bit 0 (IICRSVn) of IICA flag register n (IICFn) = 1) When bit 1 (STTn) of IICA control register n0 (IICCTLn0) is set to 1 when the bus is not used in a communication during bus communication, this request is rejected and a start condition is not generated.
Page 582 RL78/G1D CHAPTER 14 SERIAL INTERFACE IICA 14.5.15 Cautions (1) When STCENn = 0 Immediately after I C operation is enabled (IICEn = 1), the bus communication status (IICBSYn = 1) is recognized regardless of the actual bus status. When changing from a mode in which no stop condition has been detected to a master device communication mode, first generate a stop condition to release the bus, then perform master device communication.
Page 583 RL78/G1D CHAPTER 14 SERIAL INTERFACE IICA 14.5.16 Communication operations The following shows three operation procedures with the flowchart. (1) Master operation in single master system The flowchart when using the RL78/G1D as the master in a single master system is shown below. This flowchart is broadly divided into the initial settings and communication processing.
Page 584 RL78/G1D CHAPTER 14 SERIAL INTERFACE IICA (1) Master operation in single-master system Figure 14-28. Master Operation in Single-Master System START Setting the PER0 register Release the serial interface IICAn from the reset status and start clock supply. Initializing I C bus Note Setting of the port used alternatively as the pin to be used.
Page 585 RL78/G1D CHAPTER 14 SERIAL INTERFACE IICA (2) Master operation in multi-master system Figure 14-29. Master Operation in Multi-Master System (1/3) START Release the serial interface IICAn from the reset status and start clock supply. Setting the PER0 register Setting of the port used alternatively as the pin to be used. Setting port First, set the port to input mode and the output latch to 0 (see14.3.8 Port mode register 6 (PM6)).
Page 586 RL78/G1D CHAPTER 14 SERIAL INTERFACE IICA Figure 14-29. Master Operation in Multi-Master System (2/3) Enables reserving communication. Prepares for starting communication STTn = 1 (generates a start condition). Secure wait time Note by software. Wait MSTSn = 1? INTIICAn interrupt occurs? Waits for bus release (communication being reserved).
Page 587 RL78/G1D CHAPTER 14 SERIAL INTERFACE IICA Figure 14-29. Master Operation in Multi-Master System (3/3) Starts communication Writing IICAn (specifies an address and transfer direction). INTIICAn interrupt occurs? Waits for detection of ACK. MSTSn = 1? ACKDn = 1? ACKEn = 1 WTIMn = 0 TRCn = 1? WRELn = 1...
Page 588 RL78/G1D CHAPTER 14 SERIAL INTERFACE IICA (3) Slave operation The processing procedure of the slave operation is as follows. Basically, the slave operation is event-driven. Therefore, processing by the INTIICAn interrupt (processing that must substantially change the operation status such as detection of a stop condition during communication) is necessary. In the following explanation, it is assumed that the extension code is not supported for data communication.
Page 589 RL78/G1D CHAPTER 14 SERIAL INTERFACE IICA The main processing of the slave operation is explained next. Start serial interface IICA and wait until communication is enabled. When communication is enabled, execute communication by using the communication mode flag and ready flag (processing of the stop condition and start condition is performed by an interrupt.
Page 590 RL78/G1D CHAPTER 14 SERIAL INTERFACE IICA An example of the processing procedure of the slave with the INTIICAn interrupt is explained below (processing is performed assuming that no extension code is used). The INTIICAn interrupt checks the status, and the following operations are performed.
Page 591 RL78/G1D CHAPTER 14 SERIAL INTERFACE IICA (1) Master device operation (a) Start ~ Address ~ Data ~ Data ~ Stop (transmission/reception) (i) When WTIMn = 0 SPTn = 1 ↓ AD6 to AD0 R/W ACK D7 to D0 D7 to D0 1: IICSn = 1000×110B 2: IICSn = 1000×000B Note...
Page 592 RL78/G1D CHAPTER 14 SERIAL INTERFACE IICA (b) Start ~ Address ~ Data ~ Start ~ Address ~ Data ~ Stop (restart) (i) When WTIMn = 0 STTn = 1 SPTn = 1 ↓ ↓ AD6 to AD0 R/W ACK D7 to D0 AD6 to AD0 D7 to D0 1: IICSn = 1000×110B...
Page 593 RL78/G1D CHAPTER 14 SERIAL INTERFACE IICA (c) Start ~ Code ~ Data ~ Data ~ Stop (extension code transmission) (i) When WTIMn = 0 1: IICSn = 1010×110B 2: IICSn = 1010×000B Note 3: IICSn = 1010×000B (Sets the WTIMn bit to 1) 4: IICSn = 1010××00B (Sets the SPTn bit to 1) 5: IICSn = 00000001B Note To generate a stop condition, set the WTIMn bit to 1 and change the timing for generating the INTIICAn...
Page 594 RL78/G1D CHAPTER 14 SERIAL INTERFACE IICA (2) Slave device operation (slave address data reception) (a) Start ~ Address ~ Data ~ Data ~ Stop (i) When WTIMn = 0 AD6 to AD0 R/W ACK D7 to D0 D7 to D0 1: IICSn = 0001×110B 2: IICSn = 0001×000B 3: IICSn = 0001×000B...
Page 595 RL78/G1D CHAPTER 14 SERIAL INTERFACE IICA (b) Start ~ Address ~ Data ~ Start ~ Address ~ Data ~ Stop (i) When WTIMn = 0 (after restart, matches with SVAn) AD6 to AD0 R/W ACK D7 to D0 AD6 to AD0 D7 to D0 1: IICSn = 0001×110B 2: IICSn = 0001×000B...
Page 596 RL78/G1D CHAPTER 14 SERIAL INTERFACE IICA (c) Start ~ Address ~ Data ~ Start ~ Code ~ Data ~ Stop (i) When WTIMn = 0 (after restart, does not match address (= extension code)) AD6 to AD0 R/W ACK D7 to D0 AD6 to AD0 D7 to D0 1: IICSn = 0001×110B...
Page 597 RL78/G1D CHAPTER 14 SERIAL INTERFACE IICA (d) Start ~ Address ~ Data ~ Start ~ Address ~ Data ~ Stop (i) When WTIMn = 0 (after restart, does not match address (= not extension code)) AD6 to AD0 R/W ACK D7 to D0 AD6 to AD0 D7 to D0...
Page 598 RL78/G1D CHAPTER 14 SERIAL INTERFACE IICA (3) Slave device operation (when receiving extension code) The device is always participating in communication when it receives an extension code. (a) Start ~ Code ~ Data ~ Data ~ Stop (i) When WTIMn = 0 AD6 to AD0 R/W ACK D7 to D0 D7 to D0...
Page 599 RL78/G1D CHAPTER 14 SERIAL INTERFACE IICA (b) Start ~ Code ~ Data ~ Start ~ Address ~ Data ~ Stop (i) When WTIMn = 0 (after restart, matches SVAn) AD6 to AD0 R/W ACK D7 to D0 AD6 to AD0 D7 to D0 1: IICSn = 0010×010B 2: IICSn = 0010×000B...
Page 600 RL78/G1D CHAPTER 14 SERIAL INTERFACE IICA (c) Start ~ Code ~ Data ~ Start ~ Code ~ Data ~ Stop (i) When WTIMn = 0 (after restart, extension code reception) AD6 to AD0 R/W ACK D7 to D0 AD6 to AD0 D7 to D0 1: IICSn = 0010×010B 2: IICSn = 0010×000B...
Page 601 RL78/G1D CHAPTER 14 SERIAL INTERFACE IICA (d) Start ~ Code ~ Data ~ Start ~ Address ~ Data ~ Stop (i) When WTIMn = 0 (after restart, does not match address (= not extension code)) AD6 to AD0 R/W ACK D7 to D0 AD6 to AD0 D7 to D0...
Page 602 RL78/G1D CHAPTER 14 SERIAL INTERFACE IICA (4) Operation without communication (a) Start ~ Code ~ Data ~ Data ~ Stop AD6 to AD0 R/W ACK D7 to D0 D7 to D0 1: IICSn = 00000001B Remark : Generated only when SPIEn = 1 (5) Arbitration loss operation (operation as slave after arbitration loss) When the device is used as a master in a multi-master system, read the MSTSn bit each time interrupt request signal INTIICAn has occurred to check the arbitration result.
Page 603 RL78/G1D CHAPTER 14 SERIAL INTERFACE IICA (ii) When WTIMn = 1 AD6 to AD0 R/W ACK D7 to D0 D7 to D0 1: IICSn = 0101×110B 2: IICSn = 0001×100B 3: IICSn = 0001××00B 4: IICSn = 00000001B Remark : Always generated : Generated only when SPIEn = 1 ×: Don’t care...
Page 604 RL78/G1D CHAPTER 14 SERIAL INTERFACE IICA (ii) When WTIMn = 1 AD6 to AD0 R/W ACK D7 to D0 D7 to D0 1: IICSn = 0110×010B 2: IICSn = 0010×110B 3: IICSn = 0010×100B 4: IICSn = 0010××00B 5: IICSn = 00000001B Remark : Always generated : Generated only when SPIEn = 1...
Page 605 RL78/G1D CHAPTER 14 SERIAL INTERFACE IICA (b) When arbitration loss occurs during transmission of extension code AD6 to AD0 R/W ACK D7 to D0 D7 to D0 1: IICSn = 0110×010B Sets LRELn = 1 by software 2: IICSn = 00000001B Remark : Always generated : Generated only when SPIEn = 1...
Page 606 RL78/G1D CHAPTER 14 SERIAL INTERFACE IICA (ii) When WTIMn = 1 AD6 to AD0 R/W ACK D7 to D0 D7 to D0 1: IICSn = 10001110B 2: IICSn = 01000100B 3: IICSn = 00000001B Remark : Always generated : Generated only when SPIEn = 1 (d) When loss occurs due to restart condition during data transfer (i) Not extension code (Example: unmatches with SVAn) AD6 to AD0 R/W ACK...
Page 607 RL78/G1D CHAPTER 14 SERIAL INTERFACE IICA (ii) Extension code AD6 to AD0 R/W ACK D7 to Dm AD6 to AD0 D7 to D0 1: IICSn = 1000×110B 2: IICSn = 01100010B Sets LRELn = 1 by software 3: IICSn = 00000001B Remark : Always generated : Generated only when SPIEn = 1...
Page 608 RL78/G1D CHAPTER 14 SERIAL INTERFACE IICA (f) When arbitration loss occurs due to low-level data when attempting to generate a restart condition (i) When WTIMn = 0 STTn = 1 ↓ AD6 to AD0 R/W ACK D7 to D0 D7 to D0 D7 to D0 1: IICSn = 1000×110B 2: IICSn = 1000×000B (Sets the WTIMn bit to 1)
Page 609 RL78/G1D CHAPTER 14 SERIAL INTERFACE IICA (g) When arbitration loss occurs due to a stop condition when attempting to generate a restart condition (i) When WTIMn = 0 STTn = 1 ↓ AD6 to AD0 R/W ACK D7 to D0 1: IICSn = 1000×110B 2: IICSn = 1000×000B (Sets the WTIMn bit to 1) 3: IICSn = 1000××00B (Sets the STTn bit to 1)
Page 610 RL78/G1D CHAPTER 14 SERIAL INTERFACE IICA (h) When arbitration loss occurs due to low-level data when attempting to generate a stop condition (i) When WTIMn = 0 SPTn = 1 ↓ AD6 to AD0 R/W ACK D7 to D0 D7 to D0 D7 to D0 1: IICSn = 1000×110B 2: IICSn = 1000×000B (Sets the WTIMn bit to 1)
Page 611 RL78/G1D CHAPTER 14 SERIAL INTERFACE IICA 14.6 Timing Charts When using the I C bus mode, the master device outputs an address via the serial bus to select one of several slave devices as its communication partner. After outputting the slave address, the master device transmits the TRCn bit (bit 3 of the IICA status register n (IICSn)), which specifies the data transfer direction, and then starts serial communication with the slave device.
Page 612 RL78/G1D CHAPTER 14 SERIAL INTERFACE IICA Figure 14-32. Example of Master to Slave Communication (9-Clock Wait Is Selected for Master, 9-Clock Wait Is Selected for Slave) (1/4) (a) Start condition ~ address ~ data Master side Note 1 IICAn <2> <5>...
Page 613 RL78/G1D CHAPTER 14 SERIAL INTERFACE IICA The meanings of <1> to <6> in (a) Start condition ~ address ~ data in Figure 14-32 are explained below. <1> The start condition trigger is set by the master device (STTn = 1) and a start condition (i.e. SCLAn = 1 changes SDAAn from 1 to 0) is generated once the bus data line goes low (SDAAn).
Page 614 RL78/G1D CHAPTER 14 SERIAL INTERFACE IICA Figure 14-32. Example of Master to Slave Communication (9-Clock Wait Is Selected for Master, 9-Clock Wait Is Selected for Slave) (2/4) (b) Address ~ data ~ data Master side Note 1 Note 1 IICAn <5>...
Page 615 RL78/G1D CHAPTER 14 SERIAL INTERFACE IICA The meanings of <3> to <10> in (b) Address ~ data ~ data in Figure 14-32 are explained below. Note <3> In the slave device if the address received matches the address (SVAn value) of a slave device , that slave device sends an ACK by hardware to the master device.
Page 616 RL78/G1D CHAPTER 14 SERIAL INTERFACE IICA Figure 14-32. Example of Master to Slave Communication (9-Clock Wait Is Selected for Master, 9-Clock Wait Is Selected for Slave) (3/4) (c) Data ~ data ~ Stop condition Master side Note 1 IICAn <9> ACKDn (ACK detection) WTIMn...
Page 617 RL78/G1D CHAPTER 14 SERIAL INTERFACE IICA The meanings of <7> to <15> in (c) Data ~ data ~ stop condition in Figure 14-32 are explained below. <7> After data transfer is completed, because of ACKEn = 1, the slave device sends an ACK by hardware to the master device.
Page 618 RL78/G1D CHAPTER 14 SERIAL INTERFACE IICA Figure 14-32. Example of Master to Slave Communication (9-Clock Wait Is Selected for Master, 9-Clock Wait Is Selected for Slave) (4/4) (d) Data ~ restart condition ~ address Master side IICAn <iii> ACKDn (ACK detection) WTIMn (8 or 9 clock wait) ACKEn...
Page 619 RL78/G1D CHAPTER 14 SERIAL INTERFACE IICA The following describes the operations in Figure 14-32 (d) Data ~ restart condition ~ address. After the operations in steps <7> and <8>, the operations in steps <i> to <iii> are performed. These steps return the processing to step <iii>, the data transmission step.
Page 620 RL78/G1D CHAPTER 14 SERIAL INTERFACE IICA Figure 14-33. Example of Slave to Master Communication (8-Clock Wait Is Selected for Master, 9-Clock Wait Is Selected for Slave) (1/3) (a) Start condition ~ address ~ data Master side IICAn <2> ACKDn (ACK detection) WTIMn <5>...
Page 621 RL78/G1D CHAPTER 14 SERIAL INTERFACE IICA The meanings of <1> to <7> in (a) Start condition ~ address ~ data in Figure 14-33 are explained below. <1> The start condition trigger is set by the master device (STTn = 1) and a start condition (i.e. SCLAn =1 changes SDAAn from 1 to 0) is generated once the bus data line goes low (SDAAn).
Page 622 RL78/G1D CHAPTER 14 SERIAL INTERFACE IICA Figure 14-33. Example of Slave to Master Communication (8-Clock Wait Is Selected for Master, 9-Clock Wait Is Selected for Slave) (2/3) (b) Address ~ data ~ data Master side IICAn ACKDn (ACK detection) WTIMn <5>...
Page 623 RL78/G1D CHAPTER 14 SERIAL INTERFACE IICA The meanings of <3> to <12> in (b) Address ~ data ~ data in Figure 14-33 are explained below. Note <3> In the slave device if the address received matches the address (SVAn value) of a slave device , that slave device sends an ACK by hardware to the master device.
Page 624 RL78/G1D CHAPTER 14 SERIAL INTERFACE IICA Figure 14-33. Example of Slave to Master Communication (8-Clock and 9-Clock Wait Is Selected for Master, 9-Clock Wait Is Selected for Slave) (3/3) (c) Data ~ data ~ stop condition Master side IICAn ACKDn (ACK detection) WTIMn (8 or 9 clock wait)
Page 625 RL78/G1D CHAPTER 14 SERIAL INTERFACE IICA The meanings of <8> to <19> in (c) Data ~ data ~ stop condition in Figure 14-33 are explained below. <8> The master device sets a wait status (SCLAn = 0) at the falling edge of the 8th clock, and issues an interrupt (INTIICAn: end of transfer).
Page 626 United States: FCC CFR47 Sections 15.247 and 15.249 Europe: EN300 440 and EN 300 328 The contents of this chapter are in accord with the settings for operations by the Bluetooth Low Energy protocol stack from Renesas. R01UH0515EJ0120 Rev.1.20 Dec 16, 2016...
Page 627 RL78/G1D CHAPTER 15 RF TRANSCEIVER 15.1 Overview of RF Transceiver The RF transceiver supports the Bluetooth ver.4.1 Specification (low energy, single mode). The analog block consists of a low noise amplifier (LNA), mixer, ADC, power amplifier (PA), and frequency synthesizer (PLL).
Page 628 32.768-kHz input to this pin is required. In this case, the Bluetooth low Energy software stack from Renesas sets up sub-clock output (32.768 kHz) through the PCLBUZ0 pin to provide a square wave for input to EXSLK_RF. Accordingly, this pin and the PCLBUZ0 pin must be connected, and the XT1 and XT2 pins must be connected to a 32.768-kHz crystal resonator on the user...
Page 629 RL78/G1D CHAPTER 15 RF TRANSCEIVER 15.2.2 Analog pins The following describes the analog pin related to the RF transceiver. (1) ANT This is the single RF input/output pin for the RF transceiver. It is for connection to a microstripline, which should have an impedance of 50 Ω.
Page 630 RL78/G1D CHAPTER 15 RF TRANSCEIVER 15.3 Configuration of RF Transceiver The RF transceiver consists of an analog block, digital block, power management block, wakeup circuit block, RF clock generator block, and RF reset circuit block. Figure 15-1 shows a block diagram. Details are explained in the following pages.
Page 631 RL78/G1D CHAPTER 15 RF TRANSCEIVER 15.3.1 Digital block The digital blocks consist of a baseband block, an interface block, an RF memory block, an RF control block, and a modem block. Figure 15-2. Block Diagram of Baseband Block Timing Baseband control Interrupt generator generator...
Page 632 RL78/G1D CHAPTER 15 RF TRANSCEIVER (9) Radio controller Controls the RF transmission/reception circuit block. (10) Whitening Decodes the whitening of the transmit data and the whitening of the receive data. (11) Timing generator Controls the timing of the baseband. (12) Interrupt generator Controls interrupts.
Page 633 The PHY block register area has registers for setting the PHY block operation and notifying events. The baseband control register area has registers for setting the baseband block operation and notifying events. Settings are made in these memory map areas through access by the Bluetooth Low Energy protocol stack from Renesas. Figure 15-3. RF Memory Map...
Page 634 RL78/G1D CHAPTER 15 RF TRANSCEIVER 15.3.6 Analog block The analog block consists of the circuits for RF transmission and reception. Figure15-4 shows a block diagram of the RF transmission/reception circuit block. Figure15-4. RF Transmission/Reception Circuit Block Filter RFSW (1) RFSW When the analog block is operating as a transmitter, the output from the power amplifier (PA) in the transmitter section is sent to the antenna.
Page 635 RL78/G1D CHAPTER 15 RF TRANSCEIVER (7) PLL Based on the RF base clock, this generates the carrier frequency (2.4-GHz band) to be used in transmission and reception, and supplies 4-phase signals which are each shifted by 90 degrees to MIX and single-ended and single- phase signals to PA.
Page 636 RL78/G1D CHAPTER 15 RF TRANSCEIVER 15.3.9 RF clock generator circuit block The RF clock generator circuit block generates and outputs a clock signal for supply to the internal circuits of the RF unit. This block consists of the RF base clock and RF slow clock generator circuits described below. (1) RF base clock generator •...
Page 637 RL78/G1D CHAPTER 15 RF TRANSCEIVER 15.4 RF Modes 15.4.1 RF operation modes There are the following seven modes for the RF operation mode. Figure 15-5. List of RF Operating Modes (5) RF transmission mode (1) With adaptivity switched off (4) RF normal mode (6) RF reception mode (7) SETUP_RF mode (5) RF transmission mode...
Page 638 RL78/G1D CHAPTER 15 RF TRANSCEIVER (5) RF transmission mode This mode is for transmitting packets. After going through SETUP_RF mode, a packet is transmitted at the transmission timing of the event period. After packet transmission has been completed, IDLE_RF mode is entered automatically.
Page 639 RL78/G1D CHAPTER 15 RF TRANSCEIVER (3) STANDBY_RF mode On entering this mode, operation of the oscillating circuit for the RF base clock and the DC-DC converter is possible. After this mode is entered, the wait time for oscillation stabilization and DC-DC converter output stabilization is required.
Page 640 RL78/G1D CHAPTER 15 RF TRANSCEIVER 15.4.3 State transition diagram Figure 15-6 shows the state transition diagram of the RF modes of the RF transceiver. Figure 15-6. State Transition Diagram Power Power supply is started RFCTLEN pin: Low POWER_ DOWN mode RFCTLEN pin: Low →...
Page 641 RL78/G1D CHAPTER 15 RF TRANSCEIVER 15.4.4 Mode transition time Table 15-2 shows the mode transition time. Table 15-2. Mode Transition Time Mode Transition Transition Time Exit from Entry to Power off POWER_DOWN The signal on the RFCTLEN pin being at the low level for two cycles of the RF slow clock after the power-supply voltage has 1.6 V from 0 V POWER_DOWN RESET_RF...
Page 642 RL78/G1D CHAPTER 15 RF TRANSCEIVER 15.4.5 Pin status in each mode Table 15-3 shows the pin status in each operation mode. Table 15-3. Pin Status in Each Operation Mode (1/2) POWER_DOWN RESET_RF STANDBY_RF IDLE_RF SETUP_RF RFCTLEN Low-level input High-level input High-level input High-level input High-level input...
Page 643 RL78/G1D CHAPTER 15 RF TRANSCEIVER 15.4.6 Function status in each mode Table 15-4 shows the function status in each operation mode. Table 15-4. Function Status in Each Operation Mode (1/2) Function POWER_DOWN RESET_RF STANDBY_RF IDLE_RF SETUP_RF Regulator for RF Operation disabled Operation disabled Operating Operating...
Page 644 RL78/G1D CHAPTER 15 RF TRANSCEIVER Table 15-4. Function Status in Each Operation Mode (2/2) Function RF Transmission RF Reception SLEEP_RF DEEP_SLEEP Regulator for RF Operating Operating Operating Operating (partly) oscillation circuit Regulator for PLL circuit Operating Operating Operation stopped Operation stopped Regulator for ADC Operating Operating...
Page 645 RL78/G1D CHAPTER 16 MULTIPLIER AND DIVIDER/MULTIPLY-ACCUMULATOR CHAPTER 16 MULTIPLIER AND DIVIDER/MULTIPLY-ACCUMULATOR 16.1 Functions of Multiplier and Divider/Multiply-Accumulator The multiplier and divider/multiply-accumulator has the following functions. • 16 bits × 16 bits = 32 bits (Unsigned) • 16 bits × 16 bits = 32 bits (Signed) •...
Page 646 RL78/G1D CHAPTER 16 MULTIPLIER AND DIVIDER/MULTIPLY-ACCUMULATOR Figure 16-1. Block Diagram of Multiplier and Divider/Multiply-Accumulator Internal bus Multiply- Multiplication result (product) or accumulation Division multiplication result (product) while in Multiplication/division result Division result result multiply-accumulator mode (accumulated) (quotient) control register (MDUC) (remainder) Multiplication/division data register B Multiplication/division data register C...
Page 647 RL78/G1D CHAPTER 16 MULTIPLIER AND DIVIDER/MULTIPLY-ACCUMULATOR 16.2.1 Multiplication/division data register A (MDAH, MDAL) The MDAH and MDAL registers set the values that are used for a multiplication or division operation and store the operation result. They set the multiplier and multiplicand data in the multiplication mode or multiply-accumulator mode, and set the dividend data in the division mode.
Page 648 RL78/G1D CHAPTER 16 MULTIPLIER AND DIVIDER/MULTIPLY-ACCUMULATOR 16.2.2 Multiplication/division data register B (MDBL, MDBH) The MDBH and MDBL registers set the values that are used for multiplication or division operation and store the operation result. They store the operation result (product) in the multiplication mode and multiply-accumulator mode, and set the divisor data in the division mode.
Page 649 RL78/G1D CHAPTER 16 MULTIPLIER AND DIVIDER/MULTIPLY-ACCUMULATOR 16.2.3 Multiplication/division data register C (MDCL, MDCH) The MDCH and MDCL registers are used to store the accumulated result while in the multiply-accumulator mode or the remainder of the operation result while in the division mode. These registers are not used while in the multiplication mode. The MDCH and MDCL registers can be set by a 16-bit manipulation instruction.
Page 650 RL78/G1D CHAPTER 16 MULTIPLIER AND DIVIDER/MULTIPLY-ACCUMULATOR The register configuration differs between when multiplication is executed and when division is executed, as follows. • Register configuration during multiplication <Multiplier A> <Multiplier B> <Product> MDAL (bits 15 to 0) × MDAH (bits 15 to 0) = [MDBH (bits 15 to 0), MDBL (bits 15 to 0)] •...
Page 651 RL78/G1D CHAPTER 16 MULTIPLIER AND DIVIDER/MULTIPLY-ACCUMULATOR 16.3 Register Controlling Multiplier and Divider/Multiply-Accumulator The multiplier and divider/multiply-accumulator is controlled by using the multiplication/division control register (MDUC). 16.3.1 Multiplication/division control register (MDUC) The MDUC register is an 8-bit register that controls the operation of the multiplier and divider/multiply-accumulator. The MDUC register can be set by a 1-bit or 8-bit memory manipulation instruction.
Page 652 RL78/G1D CHAPTER 16 MULTIPLIER AND DIVIDER/MULTIPLY-ACCUMULATOR Figure 16-5. Format of Multiplication/Division Control Register (MDUC) Note 1 Address: F00E8H After reset: 00H Symbol <7> <6> <3> <2> <1> <0> MDUC DIVMODE MACMODE MDSM MACOF MACSF DIVST DIVMODE MACMODE MDSM Operation mode selection Multiplication mode (unsigned) (default) Multiplication mode (signed) Multiply-accumulator mode (unsigned)
Page 653 RL78/G1D CHAPTER 16 MULTIPLIER AND DIVIDER/MULTIPLY-ACCUMULATOR 16.4 Operations of Multiplier and Divider/Multiply-Accumulator 16.4.1 Multiplication (unsigned) operation • Initial setting <1> Set the multiplication/division control register (MDUC) to 00H. <2> Set the multiplicand to multiplication/division data register A (L) (MDAL). <3> Set the multiplier to multiplication/division data register A (H) (MDAH). (There is no preference in the order of executing steps <2>...
Page 654 RL78/G1D CHAPTER 16 MULTIPLIER AND DIVIDER/MULTIPLY-ACCUMULATOR 16.4.2 Multiplication (signed) operation • Initial setting <1> Set the multiplication/division control register (MDUC) to 08H. <2> Set the multiplicand to multiplication/division data register A (L) (MDAL). <3> Set the multiplier to multiplication/division data register A (H) (MDAH). (There is no preference in the order of executing steps <2>...
Page 655 RL78/G1D CHAPTER 16 MULTIPLIER AND DIVIDER/MULTIPLY-ACCUMULATOR 16.4.3 Multiply-accumulation (unsigned) operation • Initial setting <1> Set the multiplication/division control register (MDUC) to 40H. <2> Set the initial accumulated value of higher 16 bits to multiplication/division data register C (L) (MDCL). <3> Set the initial accumulated value of lower 16 bits to multiplication/division data register C (H) (MDCH). <4>...
Page 656 RL78/G1D CHAPTER 16 MULTIPLIER AND DIVIDER/MULTIPLY-ACCUMULATOR Figure 16-8. Timing Diagram of Multiply-Accumulation (Unsigned) Operation → (2 × 3 + 3 = 9 32767 × 2 + 4294901762 = 0 (over flow generated)) Operation clock <1> MDUC MDSM L MDCH 0000H FFFFH 0000H MDCL...
Page 657 RL78/G1D CHAPTER 16 MULTIPLIER AND DIVIDER/MULTIPLY-ACCUMULATOR 16.4.4 Multiply-accumulation (signed) operation • Initial setting <1> Set the multiplication/division control register (MDUC) to 48H. <2> Set the initial accumulated value of higher 16 bits to multiplication/division data register C (H) (MDCH). (<3> If the accumulated value in the MDCH register is negative, the MACSF bit is set to 1.) <4>...
Page 658 RL78/G1D CHAPTER 16 MULTIPLIER AND DIVIDER/MULTIPLY-ACCUMULATOR Figure 16-9. Timing Diagram of Multiply-Accumulation (signed) Operation → (2 × 3 + (–4) = 2 32767 × (–1) + (–2147483647) = –2147450882 (overflow occurs.)) Operation clock <1> MDUC MDSM L <3> <9> <3> MDCH 0000H FFFFH...
Page 659 RL78/G1D CHAPTER 16 MULTIPLIER AND DIVIDER/MULTIPLY-ACCUMULATOR 16.4.5 Division operation • Initial setting <1> Set the multiplication/division control register (MDUC) to 80H. <2> Set the dividend (higher 16 bits) to multiplication/division data register A (H) (MDAH). <3> Set the dividend (lower 16 bits) to multiplication/division data register A (L) (MDAL). <4>...
Page 660 RL78/G1D CHAPTER 16 MULTIPLIER AND DIVIDER/MULTIPLY-ACCUMULATOR R01UH0515EJ0120 Rev.1.20 Dec 16, 2016...
Page 661 RL78/G1D CHAPTER 17 DMA CONTROLLER CHAPTER 17 DMA CONTROLLER The RL78/G1D has an internal DMA (Direct Memory Access) controller. Data can be automatically transferred between the peripheral hardware supporting DMA, SFRs, and internal RAM without via CPU. As a result, the normal internal operation of the CPU and data transfer can be executed in parallel with transfer between the SFR and internal RAM, and therefore, a large capacity of data can be processed.
Page 662 RL78/G1D CHAPTER 17 DMA CONTROLLER 17.2 Configuration of DMA Controller The DMA controller includes the following hardware. Table 17-1. Configuration of DMA Controller Item Configuration Address registers ● DMA SFR address registers 0 to 3 (DSA0 to DSA3) ● DMA RAM address registers 0 to 3 (DRA0 to DRA3) Count register ●...
Page 663 RL78/G1D CHAPTER 17 DMA CONTROLLER 17.2.2 DMA RAM address register n (DRAn) This is a 16-bit register that is used to set a RAM address that is the transfer source or destination of DMA channel n. Addresses of the internal RAM area other than the general-purpose registers (see Table 17-2) can be set to this register.
Page 664 RL78/G1D CHAPTER 17 DMA CONTROLLER 17.2.3 DMA byte count register n (DBCn) This is a 10-bit register that is used to set the number of times DMA channel n executes transfer. Be sure to set the number of times of transfer to this DBCn register before executing DMA transfer (up to 1024 times). Each time DMA transfer has been executed, this register is automatically decremented.
Page 665 RL78/G1D CHAPTER 17 DMA CONTROLLER 17.3 Registers Controlling DMA Controller DMA controller is controlled by the following registers. ● DMA mode control register n (DMCn) ● DMA operation control register n (DRCn) Remark n: DMA channel number (n = 0 to 3) R01UH0515EJ0120 Rev.1.20 Dec 16, 2016...
Page 666 RL78/G1D CHAPTER 17 DMA CONTROLLER 17.3.1 DMA mode control register n (DMCn) The DMCn register is a register that is used to set a transfer mode of DMA channel n. It is used to select a transfer direction, data size, setting of pending, and start source. Bit 7 (STGn) is a software trigger that starts DMA. Rewriting bits 6, 5, and 3 to 0 of the DMCn register is prohibited during operation (when DSTn = 1).
Page 667 RL78/G1D CHAPTER 17 DMA CONTROLLER Figure 17-4. Format of DMA Mode Control Register n (DMCn) (2/3) Address: FFFBAH (DMC0), FFFBBH (DMC1) After reset: 00H Symbol <7> <6> <5> <4> DMCn STGn DRSn DWAITn IFCn3 IFCn2 IFCn1 IFCn0 (When n = 0 or 1) Note IFCn IFCn...
Page 668 RL78/G1D CHAPTER 17 DMA CONTROLLER Figure 17-4. Format of DMA Mode Control Register n (DMCn) (3/3) Address: F020AH (DMC2), F020BH (DMC3) After reset: 00H Symbol <7> <6> <5> <4> DMCn STGn DRSn DWAITn IFCn3 IFCn2 IFCn1 IFCn0 (When n = 2 or 3) Note IFCn IFCn...
Page 669 RL78/G1D CHAPTER 17 DMA CONTROLLER 17.3.2 DMA operation control register n (DRCn) The DRCn register is a register that is used to enable or disable transfer of DMA channel n. Rewriting bit 7 (DENn) of this register is prohibited during operation (when DSTn = 1). The DRCn register can be set by a 1-bit or 8-bit memory manipulation instruction.
Page 670 RL78/G1D CHAPTER 17 DMA CONTROLLER 17.4 Operation of DMA Controller 17.4.1 Operation procedure <1> The DMA controller is enabled to operate when DENn = 1. Before writing the other registers, be sure to set the DENn bit to 1. Use 80H to write with an 8-bit manipulation instruction. <2>...
Page 671 RL78/G1D CHAPTER 17 DMA CONTROLLER 17.4.2 Transfer mode The following four modes can be selected for DMA transfer by using bits 6 and 5 (DRSn and DSn) of DMA mode control register n (DMCn). DRSn DMA Transfer Mode Transfer from SFR of 1-byte data (fixed address) to RAM (address is incremented by +1) Transfer from SFR of 2-byte data (fixed address) to RAM (address is incremented by +2) Transfer from RAM of 1-byte data (address is incremented by +1) to SFR (fixed address) Transfer from RAM of 2-byte data (address is incremented by +2) to SFR (fixed address)
Page 672 RL78/G1D CHAPTER 17 DMA CONTROLLER 17.5 Example of Setting of DMA Controller 17.5.1 CSI consecutive transmission A flowchart showing an example of setting for CSI consecutive transmission is shown below. ● Consecutive transmission of CSI20 (256 bytes) ● DMA channel 0 is used for DMA transfer. ●...
Page 673 RL78/G1D CHAPTER 17 DMA CONTROLLER Figure 17-7. Example of Setting for CSI Consecutive Transmission Start DEN0 = 1 DSA0 = 48H DRA0 = FB00H DBC0 = 0100H DMC0 = 48H Setting for CSI transfer DST0 = 1 DMA is started. STG0 = 1 INTCSI20 occurs.
Page 674 RL78/G1D CHAPTER 17 DMA CONTROLLER 17.5.2 Consecutive capturing of A/D conversion results A flowchart of an example of setting for consecutively capturing A/D conversion results is shown below. ● Consecutive capturing of A/D conversion results. ● DMA channel 1 is used for DMA transfer. ●...
Page 675 RL78/G1D CHAPTER 17 DMA CONTROLLER Figure 17-8. Example of Setting of Consecutively Capturing A/D Conversion Results Start DEN1 = 1 DSA1 = 1EH DRA1 = FCE0H DBC1 = 0100H DMC1 = 21H DST1 = 1 Starting A/D conversion INTAD occurs. User program processing DMA1 transfer...
Page 676 RL78/G1D CHAPTER 17 DMA CONTROLLER 17.5.3 UART consecutive reception + ACK transmission A flowchart illustrating an example of setting for UART consecutive reception + ACK transmission is shown below. ● Consecutively receives data from UART0 and outputs ACK to P10 on completion of reception. ●...
Page 677 RL78/G1D CHAPTER 17 DMA CONTROLLER Figure 17-9. Example of Setting UART Consecutive Reception + ACK Transmission Start INTSR0 interrupt routine DEN0 = 1 DSA0 = 12H DRA0 = FE00H DBC0 = 0040H DMA0 is started. DMC0 = 00H STG0 = 1 DMA0 transfer P10 = 1 Setting for UART reception...
Page 678 RL78/G1D CHAPTER 17 DMA CONTROLLER 17.5.4 Holding DMA transfer pending by DWAITn bit When DMA transfer is started, transfer is performed while an instruction is executed. At this time, the operation of the CPU is stopped and delayed for the duration of 2 clocks. If this poses a problem to the operation of the set system, a DMA transfer can be held pending by setting the DWAITn bit to 1.
Page 679 RL78/G1D CHAPTER 17 DMA CONTROLLER 17.5.5 Forced termination by software After the DSTn bit is set to 0 by software, it takes up to 2 clocks until a DMA transfer is actually stopped and the DSTn bit is set to 0. To forcibly terminate a DMA transfer by software without waiting for occurrence of the interrupt (INTDMAn) of DMAn, therefore, perform either of the following processes.
Page 680 RL78/G1D CHAPTER 17 DMA CONTROLLER Figure 17-11. Forced Termination of DMA Transfer (2/2) Example 3 ● Procedure for forcibly terminating the DMA ● Procedure for forcibly terminating the DMA transfer for one channel if both channels are used transfer for both channels if both channels are used DWAIT0 = 1 DWAIT0 = 1 DWAIT1 = 1...
Page 681 RL78/G1D CHAPTER 17 DMA CONTROLLER 17.6 Cautions on Using DMA Controller (1) Priority of DMA During DMA transfer, a request from the other DMA channel is held pending even if generated. The pending DMA transfer is started after the ongoing DMA transfer is completed. If two or more DMA requests are generated at the same time, however, their priority is DMA channel 0 >...
Page 682 RL78/G1D CHAPTER 17 DMA CONTROLLER (5) DMA pending instruction Even if a DMA request is generated, DMA transfer is held pending immediately after the instructions given below. ● CALL !addr16 ● CALL $!addr20 ● CALL !!addr20 ● CALL ● CALLT [addr5] ●...
Page 683 RL78/G1D CHAPTER 17 DMA CONTROLLER (7) Operation if instructions for accessing the data flash area If the data flash area is accessed after an next instruction execution from start of DMA transfer, a 3-clock wait will be inserted to the next instruction. Instruction 1 DMA transfer Instruction 2...
Page 684 RL78/G1D CHAPTER 18 INTERRUPT FUNCTIONS CHAPTER 18 INTERRUPT FUNCTIONS The interrupt function switches the program execution to other processing. When the branch processing is finished, the program returns to the interrupted processing. There are four external interrupt sources and 29 internal interrupt sources. 18.1 Interrupt Function Types The following two types of interrupt functions are used.
Page 685 RL78/G1D CHAPTER 18 INTERRUPT FUNCTIONS 18.2 Interrupt Sources and Configuration Interrupt sources include maskable interrupts and software interrupts. In addition, they also have up to seven reset sources (see Table 18-1). The vector codes that store the program start address when branching due to the generation of a reset or various interrupt requests are two bytes each, so interrupts jump to a 64 K address of 00000H to 0FFFFH.
Page 686 RL78/G1D CHAPTER 18 INTERRUPT FUNCTIONS Table 18-1. Interrupt Source List (2/3) Interrupt Internal/ Vector Interrupt Source Type External Table Name Trigger Address Maskable INTSRE1 UART1 reception communication Internal 0028H error occurrence INTTM03H End of timer channel 03 count or capture (at lower 8-bit timer operation) INTIICA0 IICA0 transfer end...
Page 687 RL78/G1D CHAPTER 18 INTERRUPT FUNCTIONS Table 18-1. Interrupt Source List (3/3) Interrupt Internal/ Vector Interrupt Source Type External Table Name Trigger Address Software – Execution of BRK instruction – 007EH Reset – RESET RESET pin input – 0000H – Power-on-reset Note 3 Voltage detection Overflow of watchdog timer...
Page 688 RL78/G1D CHAPTER 18 INTERRUPT FUNCTIONS Figure 18-1. Basic Configuration of Interrupt Function (1/2) (A) Internal maskable interrupt Internal bus ISP1 ISP0 Vector table Interrupt Priority controller address generator request Standby release signal (B) External maskable interrupt (INTPn) Internal bus External interrupt edge enable register ISP1 ISP0...
Page 689 RL78/G1D CHAPTER 18 INTERRUPT FUNCTIONS Figure 18-1. Basic Configuration of Interrupt Function (2/2) (C) Software interrupt Internal bus Interrupt Vector table request address generator R01UH0515EJ0120 Rev.1.20 Dec 16, 2016...
Page 690 RL78/G1D CHAPTER 18 INTERRUPT FUNCTIONS 18.3 Registers Controlling Interrupt Functions The following 6 types of registers are used to control the interrupt functions. ● Interrupt request flag registers (IF0L, IF0H, IF1L, IF1H, IF2L, IF2H, IF3L) ● Interrupt mask flag registers (MK0L, MK0H, MK1L, MK1H, MK2L, MK2H, MK3L) ●...
Page 691 RL78/G1D CHAPTER 18 INTERRUPT FUNCTIONS Table 18-2. Flags Corresponding to Interrupt Request Sources (2/2) Interrupt Interrupt Request Flag Interrupt Mask Flag Priority Specification Flag Source Register Register Register INTST1 STIF1 IF1L STMK1 STMK1 STPR01, STPR11 PR01L, PR11L INTSR1 SRIF1 SRMK1 SRPR01, SRPR11 Note Note...
Page 692 RL78/G1D CHAPTER 18 INTERRUPT FUNCTIONS 18.3.1 Interrupt request flag registers (IF0L, IF0H, IF1L, IF1H, IF2L, IF2H, IF3L) The interrupt request flags are set to 1 when the corresponding interrupt request is generated or an instruction is executed. They are cleared to 0 when an instruction is executed upon acknowledgment of an interrupt request or upon reset signal generation.
Page 693 RL78/G1D CHAPTER 18 INTERRUPT FUNCTIONS Figure 18-2. Format of Interrupt Request Flag Registers (IF0L, IF0H, IF1L, IF1H, IF2L, IF2H, IF3L) (2/2) Address: FFFD1H After reset: 00H Symbol <7> <5> <0> IF2H FLIF MDIF PIF11 Address: FFFD2H After reset: 00H Symbol <1>...
Page 694 RL78/G1D CHAPTER 18 INTERRUPT FUNCTIONS 18.3.2 Interrupt mask flag registers (MK0L, MK0H, MK1L, MK1H, MK2L, MK2H, MK3L) The interrupt mask flags are used to enable/disable the corresponding maskable interrupt. The MK0L, MK0H, MK1L, MK1H, MK2L, MK2H, and MK3L registers can be set by a 1-bit or 8-bit memory manipulation instruction.
Page 695 RL78/G1D CHAPTER 18 INTERRUPT FUNCTIONS Figure 18-3. Format of Interrupt Mask Flag Registers (MK0L, MK0H, MK1L, MK1H, MK2L, MK2H, MK3L) (2/2) Address: FFFD5H After reset: FFH Symbol <7> <5> <0> MK2H FLMK MDMK PMK11 Address: FFFD6H After reset: FFH Symbol <1>...
Page 696 RL78/G1D CHAPTER 18 INTERRUPT FUNCTIONS 18.3.3 Priority specification flag registers (PR00L, PR00H, PR01L, PR01H, PR02L, PR02H, PR03L, PR10L, PR10H, PR11L, PR11H, PR12L, PR12H, PR13L) The priority specification flag registers are used to set the corresponding maskable interrupt priority level. A priority level is set by using the PR0xy and PR1xy registers in combination (xy = 0L, 0H, 1L, 1H, 2L, or 2H). The PR00L, PR00H, PR01L, PR01H, PR02L, PR02H, PR03L, PR10L, PR10H, PR11L, PR11H, PR12L, PR12H, and the PR13L registers can be set by a 1-bit or 8-bit memory manipulation instruction.
Page 697 RL78/G1D CHAPTER 18 INTERRUPT FUNCTIONS Figure 18-4. Format of Priority Specification Flag Registers (PR00L, PR00H, PR01L, PR01H, PR02L, PR02H, PR03L, PR10L, PR10H, PR11L, PR11H, PR12L, PR12H, PR13L) (2/3) Address: FFFEBH After reset: FFH Symbol <7> <2> <1> <0> PR01H TMPR004 ITPR0 RTCPR0 ADPR0...
Page 698 RL78/G1D CHAPTER 18 INTERRUPT FUNCTIONS Figure 18-4. Format of Priority Specification Flag Registers (PR00L, PR00H, PR01L, PR01H, PR02L, PR02H, PR03L, PR10L, PR10H, PR11L, PR11H, PR12L, PR12H, PR13L) (3/3) Address: FFFDAH After reset: FFH Symbol <1> <0> PR03L DMAPR03 DMAPR02 Address: FFFDEH After reset: FFH Symbol <1>...
Page 699 RL78/G1D CHAPTER 18 INTERRUPT FUNCTIONS 18.3.4 External interrupt rising edge enable registers (EGP0), external interrupt falling edge enable registers (EGN0) These registers specify the valid edge for INTP0, INTP3, INTP5 and NTP6. The EGP0 and EGN0 registers can be set by a 1-bit or 8-bit memory manipulation instruction. Reset signal generation clears these registers to 00H.
Page 700 RL78/G1D CHAPTER 18 INTERRUPT FUNCTIONS 18.3.5 Program status word (PSW) The program status word is a register used to hold the instruction execution result and the current status for an interrupt request. The IE flag that sets maskable interrupt enable/disable and the ISP0 and ISP1 flags that controls multiple interrupt servicing are mapped to the PSW.
Page 701 RL78/G1D CHAPTER 18 INTERRUPT FUNCTIONS 18.4 Interrupt Servicing Operations 18.4.1 Maskable interrupt request acknowledgment A maskable interrupt request becomes acknowledgeable when the interrupt request flag is set to 1 and the mask (MK) flag corresponding to that interrupt request is cleared to 0. A vectored interrupt request is acknowledged if interrupts are in the interrupt enabled state (when the IE flag is set to 1).
Page 702 RL78/G1D CHAPTER 18 INTERRUPT FUNCTIONS Figure 18-7. Interrupt Request Acknowledgment Processing Algorithm Start ××IF = 1? Yes (interrupt request generation) ××MK = 0? Interrupt request held pending No (Low priority) (××PR ××PR ≥ (ISP1, ISP0) Interrupt request held pending Yes (High priority) Higher priority than other interrupt requests simultaneously...
Page 703 RL78/G1D CHAPTER 18 INTERRUPT FUNCTIONS Figure 18-8. Interrupt Request Acknowledgment Timing (Minimum Time) 6 clocks PSW and PC saved, Interrupt servicing jump to interrupt CPU processing Instruction Instruction program servicing xxIF 9 clocks Remark 1 clock: 1/f : CPU clock) Figure 18-9.
Page 704 RL78/G1D CHAPTER 18 INTERRUPT FUNCTIONS 18.4.2 Software interrupt request acknowledgment A software interrupt request is acknowledged by BRK instruction execution. Software interrupts cannot be disabled. If a software interrupt request is acknowledged, the contents are saved into the stacks in the order of the program status word (PSW), then program counter (PC), the IE flag is reset (0), and the contents of the vector table (0007EH, 0007FH) are loaded into the PC and branched.
Page 705 RL78/G1D CHAPTER 18 INTERRUPT FUNCTIONS Table 18-5. Relationship Between Interrupt Requests Enabled for Multiple Interrupt Servicing During Interrupt Servicing Multiple Interrupt Request Maskable Interrupt Request Software Interrupt Priority Level 0 Priority Level 1 Priority Level 2 Priority Level 3 Request (PR = 00) (PR = 01) (PR = 10)
Page 706 RL78/G1D CHAPTER 18 INTERRUPT FUNCTIONS Figure 18-10. Examples of Multiple Interrupt Servicing (1/2) Example 1. Multiple interrupt servicing occurs twice Main processing INTxx servicing INTyy servicing INTzz servicing IE = 0 IE = 0 IE = 0 INTxx INTyy INTzz (PR = 11) (PR = 10) (PR = 01)
Page 707 RL78/G1D CHAPTER 18 INTERRUPT FUNCTIONS Figure 18-10. Examples of Multiple Interrupt Servicing (2/2) Example 3. Multiple interrupt servicing does not occur because interrupts are not enabled Main processing INTxx servicing INTyy servicing IE = 0 INTyy (PR = 00) INTxx RETI (PR = 11) IE = 1...
Page 708 RL78/G1D CHAPTER 18 INTERRUPT FUNCTIONS 18.4.4 Interrupt request hold There are instructions where, even if an interrupt request is issued while the instructions are being executed, interrupt request acknowledgment is held pending until the end of execution of the next instruction. These instructions (interrupt request hold instructions) are listed below.
Page 709 RL78/G1D CHAPTER 19 STANDBY FUNCTION CHAPTER 19 STANDBY FUNCTION 19.1 Standby Function The standby function of the MCU unit reduces the operating current of the system, and the following three modes are available. (1) HALT mode HALT instruction execution sets the HALT mode. In the HALT mode, the CPU operation clock is stopped. If the high- speed system clock oscillator, high-speed on-chip oscillator, or subsystem clock oscillator is operating before the HALT mode is set, oscillation of each clock continues.
Page 710 RL78/G1D CHAPTER 19 STANDBY FUNCTION 19.2 Registers Controlling Standby Function The registers which control the standby function are described below. ● Subsystem clock supply mode control register (OSMC) ● Oscillation stabilization time counter status register (OSTC) ● Oscillation stabilization time select register (OSTS) Remark For details of registers described above, see CHAPTER 6 CLOCK GENERATOR.
Page 711 RL78/G1D CHAPTER 19 STANDBY FUNCTION Table 19-1. Operating Statuses in HALT Mode (1/2) HALT Mode Setting When HALT Instruction Is Executed While CPU Is Operating on Main System Clock When CPU Is Operating on When CPU Is Operating on When CPU Is Operating on High-speed On-chip Oscillator X1 Clock (f External Main System Clock...
Page 712 RL78/G1D CHAPTER 19 STANDBY FUNCTION Table 19-1. Operating Statuses in HALT Mode (2/2) HALT Mode Setting When HALT Instruction Is Executed While CPU Is Operating on Subsystem Clock Item When CPU Is Operating on XT1 Clock (f When CPU Is Operating on External Subsystem Clock (f System clock Clock supply to the CPU is stopped...
Page 713 RL78/G1D CHAPTER 19 STANDBY FUNCTION (2) HALT mode release The HALT mode can be released by the following two sources. (a) Release by unmasked interrupt request When an unmasked interrupt request is generated, the HALT mode is released. If interrupt acknowledgment is enabled, vectored interrupt servicing is carried out.
Page 714 RL78/G1D CHAPTER 19 STANDBY FUNCTION (b) Release by reset signal generation When the reset signal is generated, HALT mode is released, and then, as in the case with a normal reset operation, the program is executed after branching to the reset vector address. Figure 19-2.
Page 715 RL78/G1D CHAPTER 19 STANDBY FUNCTION Figure 19-2. HALT Mode Release by Reset (2/2) (c) When subsystem clock is used as CPU clock HALT instruction Reset signal Normal operation mode Normal operation Reset (high-speed on-chip Status of CPU (subsystem clock) Note HALT mode period oscillator clock)
Page 716 RL78/G1D CHAPTER 19 STANDBY FUNCTION Table 19-2. Operating Statuses in STOP Mode STOP Mode Setting When STOP Instruction Is Executed While CPU Is Operating on Main System Clock When CPU Is Operating on When CPU Is Operating on When CPU Is Operating on High-speed on-chip oscillator X1 Clock (f External Main System Clock...
Page 717 RL78/G1D CHAPTER 19 STANDBY FUNCTION (2) STOP mode release The STOP mode can be released by the following two sources. (a) Release by unmasked interrupt request When an unmasked interrupt request is generated, the STOP mode is released. After the oscillation stabilization time has elapsed, if interrupt acknowledgment is enabled, vectored interrupt servicing is carried out.
Page 718 RL78/G1D CHAPTER 19 STANDBY FUNCTION Figure 19-3. STOP Mode Release by Interrupt Request Generation (2/2) (b) When high-speed system clock (X1 oscillation) is used as CPU clock Interrupt request STOP instruction Standby release signal Note 1 STOP mode release time Note 2 Normal operation Normal operation...
Page 719 RL78/G1D CHAPTER 19 STANDBY FUNCTION (b) Release by reset signal generation When the reset signal is generated, STOP mode is released, and then, as in the case with a normal reset operation, the program is executed after branching to the reset vector address. Figure 19-4.
Page 720 RL78/G1D CHAPTER 19 STANDBY FUNCTION 19.3.3 SNOOZE mode (1) SNOOZE mode setting and operating statuses The SNOOZE mode can only be specified for CSI00, UART0, or the A/D converter. Note that this mode can only be specified if the CPU clock is the high-speed on-chip oscillator clock. When using CSI00 or UART0 in the SNOOZE mode, set the SWCm bit of the serial standby control register m (SSCm) to 1 immediately before switching to the STOP mode.
Page 721 RL78/G1D CHAPTER 19 STANDBY FUNCTION Table 19-3. Operating Statuses in SNOOZE Mode STOP Mode Setting When Inputting CSI00/UART0 Data Reception Signal or A/D Converter Timer Trigger Signal While in STOP Mode Item When CPU Is Operating on High-speed on-chip oscillator clock (f System clock Clock supply to the CPU is stopped Main system clock...
Page 722 RL78/G1D CHAPTER 19 STANDBY FUNCTION (2) Timing diagram when the interrupt request signal is generated in the SNOOZE mode Figure 19-5. When the Interrupt Request Signal is Generated in the SNOOZE Mode STOP Trigger instruction detection Interrupt request Standby release Note 1 signal Note 4...
Page 723 RL78/G1D CHAPTER 20 RESET FUNCTION CHAPTER 20 RESET FUNCTION The following seven operations are available to generate a reset signal. (1) External reset input via RESET pin (2) Internal reset by watchdog timer program loop detection (3) Internal reset by comparison of supply voltage and detection voltage of power-on-reset (POR) circuit (4) Internal reset by comparison of supply voltage of the voltage detector (LVD) and detection voltage Note (5) Internal reset by execution of illegal instruction...
Page 724 RL78/G1D CHAPTER 20 RESET FUNCTION R01UH0515EJ0120 Rev.1.20 Dec 16, 2016...
Page 725 RL78/G1D CHAPTER 20 RESET FUNCTION 20.1 Timing of Reset Operation This LSI is reset by input of the low level on the RESET pin and released from the reset state by input of the high level on the RESET pin. After reset processing, execution of the program with the high-speed on-chip oscillator clock as the operating clock starts.
Page 726 RL78/G1D CHAPTER 20 RESET FUNCTION Notes 1. When P130 is set to high-level output before reset is effected, the output signal of P130 can be dummy- output as a reset signal to an external device, because P130 outputs a low level when reset is effected. To release a reset signal to an external device, set P130 to high-level output by software.
Page 727 RL78/G1D CHAPTER 20 RESET FUNCTION 20.2 States of Operation During Reset Periods Table 20-1 shows the states of operation during reset periods. Table 20-2 shows the states of the hardware after receiving a reset signal. Table 20-1. States of Operation During Reset Period Item During Reset Period System clock...
Page 728 RL78/G1D CHAPTER 20 RESET FUNCTION Remark f High-speed on-chip oscillator clock X1 oscillation clock : External main system clock : XT1 oscillation clock : External subsystem clock Low-speed on-chip oscillator clock Table 20-2. State of Hardware After Receiving a Reset Signal Hardware After Reset Note...
Page 729 RL78/G1D CHAPTER 20 RESET FUNCTION 20.3 Register for Confirming Reset Source 20.3.1 Reset control flag register (RESF) Many internal reset generation sources exist in the RL78 microcontroller. The reset control flag register (RESF) is used to store which source has generated the reset request. The RESF register can be read by an 8-bit memory manipulation instruction.
Page 730 RL78/G1D CHAPTER 20 RESET FUNCTION The status of the RESF register when a reset request is generated is shown in Table 20-3. Table 20-3. RESF Register Status When Reset Request Is Generated Reset Source RESET Input Reset by Reset by Reset by Reset by Reset by...
Page 731 RL78/G1D CHAPTER 20 RESET FUNCTION Figure 20-5. Example of Procedure for Checking Reset Source After reset acceptance Read the RESF register (clear the RESF register) and store Read RESF register the value of the RESF register in any RAM. TRAP of RESF register = 1? Internal reset request by the execution of the illegal instruction...
Page 732 RL78/G1D CHAPTER 21 POWER-ON-RESET CIRCUIT CHAPTER 21 POWER-ON-RESET CIRCUIT 21.1 Functions of Power-on-reset Circuit The power-on-reset circuit (POR) has the following functions. ● Generates internal reset signal at power on. The reset signal is released when the supply voltage (V ) exceeds the detection voltage (V ).
Page 733 RL78/G1D CHAPTER 21 POWER-ON-RESET CIRCUIT 21.2 Configuration of Power-on-reset Circuit The block diagram of the power-on-reset circuit is shown in Figure 21-1. Figure 21-1. Block Diagram of Power-on-reset Circuit Internal reset signal Reference voltage source 21.3 Operation of Power-on-reset Circuit The timing of generation of the internal reset signal by the power-on-reset circuit and voltage detector is shown below.
Page 734 RL78/G1D CHAPTER 21 POWER-ON-RESET CIRCUIT Figure 21-2. Timing of Generation of Internal Reset Signal by Power-on-reset Circuit and Voltage Detector (1/3) (a) When the externally input reset signal on the RESET pin is used Supply voltage (V Note 5 Note 5 Lower limit voltage for guaranteed operation = 1.51 V (TYP.) = 1.50 V (TYP.)
Page 735 RL78/G1D CHAPTER 21 POWER-ON-RESET CIRCUIT Figure 21-2. Timing of Generation of Internal Reset Signal by Power-on-reset Circuit and Voltage Detector (2/3) (b) LVD interrupt & reset mode (option byte 000C1: LVIMDS1, LVIMDS0 = 1, 0) Supply voltage (V Note 3 LVDH LVDL Lower limit voltage for guaranteed operation...
Page 736 RL78/G1D CHAPTER 21 POWER-ON-RESET CIRCUIT Figure 21-2. Timing of Generation of Internal Reset Signal by Power-on-reset Circuit and Voltage Detector (3/3) (c) LVD reset mode (option byte 000C1H: LVIMDS1 = 1, LVIMDS0 = 1) Supply voltage (V Lower limit voltage for guaranteed operation = 1.51 V ( TYP.) = 1.50 V ( TYP.) Wait for oscillation...
Page 737 RL78/G1D CHAPTER 22 VOLTAGE DETECTOR CHAPTER 22 VOLTAGE DETECTOR 22.1 Functions of Voltage Detector The operation mode and detection voltages (V ) for the voltage detector is set by using the option byte LVDH LVDL (000C1H). The voltage detector (LVD) has the following functions. ●...
Page 738 RL78/G1D CHAPTER 22 VOLTAGE DETECTOR 22.2 Configuration of Voltage Detector The block diagram of the voltage detector is shown in Figure 22-1. Figure 22-1. Block Diagram of Voltage Detector N-ch Internal reset signal LVDH LVDL INTLVI Option byte (000C1H) Reference voltage LVIS1, LVIS0 source...
Page 739 RL78/G1D CHAPTER 22 VOLTAGE DETECTOR 22.3.1 Voltage detection register (LVIM) This register is used to specify whether to enable or disable rewriting the voltage detection level register (LVIS), as well as to check the LVD output mask status. This register can be set by a 1-bit or 8-bit memory manipulation instruction. Reset signal generation clears this register to 00H.
Page 740 RL78/G1D CHAPTER 22 VOLTAGE DETECTOR 22.3.2 Voltage detection level register (LVIS) This register selects the voltage detection level. This register can be set by a 1-bit or 8-bit memory manipulation instruction. Note 1 Reset signal generation input sets this register to 00H/01H/81H Figure 22-3.
Page 741 RL78/G1D CHAPTER 22 VOLTAGE DETECTOR Figure 22-4. Format of User Option Byte (000C1H/010C1H) (1/2) Note Address: 000C1H/010C1H VPOC2 VPOC1 VPOC0 LVIS1 LVIS0 LVIMDS1 LVIMDS0 ● LVD setting (interrupt & reset mode) Detection voltage Option byte setting value VPOC2 VPOC1 VPOC0 LVIS1 LVIS0 Mode setting...
Page 742 RL78/G1D CHAPTER 22 VOLTAGE DETECTOR Figure 22-4. Format of User Option Byte (000C1H/010C1H) (2/2) Note Address: 000C1H/010C1H VPOC2 VPOC1 VPOC0 LVIS1 LVIS0 LVIMDS1 LVIMDS0 ● LVD setting (interrupt mode) Detection voltage Option byte setting value VPOC2 VPOC1 VPOC0 LVIS1 LVIS0 Mode setting Rising edge Falling edge...
Page 743 RL78/G1D CHAPTER 22 VOLTAGE DETECTOR 22.4 Operation of Voltage Detector 22.4.1 When used as reset mode Specify the operation mode (the reset mode (LVIMDS1, LVIMDS0 = 1, 1)) and the detection voltage (V ) by using the option byte 000C1H. The operation is started in the following initial setting state when the reset mode is set.
Page 744 RL78/G1D CHAPTER 22 VOLTAGE DETECTOR Figure 22-5. Timing of Voltage Detector Internal Reset Signal Generation (Option Byte LVIMDS1, LVIMDS0 = 1, 1) Supply voltage (V Lower limit of operation voltage = 1.51 V (TY P.) = 1.50 V (TY P.) Time Cleared LVIF flag...
Page 745 RL78/G1D CHAPTER 22 VOLTAGE DETECTOR 22.4.2 When used as interrupt mode Specify the operation mode (the interrupt mode (LVIMDS1, LVIMDS0 = 0, 1)) and the detection voltage (V ) by using the option byte 000C1H. The operation is started in the following initial setting state when the interrupt mode is set. ●...
Page 746 RL78/G1D CHAPTER 22 VOLTAGE DETECTOR Figure 22-6. Timing of Voltage Detector Internal Interrupt Signal Generation (Option Byte LVIMDS1, LVIMDS0 = 0, 1) Note 2 Note 2 Supply voltage (V Lower limit of operation voltage = 1.51 V (TYP.) = 1.50 V (TYP.) Time Note 1 LVIMK flag...
Page 747 RL78/G1D CHAPTER 22 VOLTAGE DETECTOR 22.4.3 When used as interrupt & reset mode Specify the operation mode (the interrupt & reset (LVIMDS1, LVIMDS0 = 1, 0)) and the detection voltage (V LVDH LVDL by using the option byte 000C1H. The operation is started in the following initial setting state when the interrupt & reset mode is set. ●...
Page 748 RL78/G1D CHAPTER 22 VOLTAGE DETECTOR Figure 22-7. Timing of Voltage Detector Reset Signal and Interrupt Signal Generation (Option Byte LVIMDS1, LVIMDS0 = 1, 0) (1/2) If a reset is not generated after releasing the mask, determine that a condition of V becomes V ³...
Page 749 RL78/G1D CHAPTER 22 VOLTAGE DETECTOR Notes 1. The LVIMK flag is set to “1” by reset signal generation. After an interrupt is generated, perform the processing according to Figure 22-8 Processing Procedure After an Interrupt Is Generated. After a reset is released, perform the processing according to Figure 22-9 Initial Setting of Interrupt and Reset Mode.
Page 750 RL78/G1D CHAPTER 22 VOLTAGE DETECTOR Figure 22-7. Timing of Voltage Detector Reset Signal and Interrupt Signal Generation (Option Byte LVIMDS1, LVIMDS0 = 1, 0) (2/2) When a condition of V is V < V after releasing the mask, LVIH a reset is generated because of LVIMD = 1 (reset mode). Supply voltage (V LVDH LVDL...
Page 751 RL78/G1D CHAPTER 22 VOLTAGE DETECTOR Notes 1. The LVIMK flag is set to “1” by reset signal generation. After an interrupt is generated, perform the processing according to Figure 22-8 Processing Procedure After an Interrupt Is Generated. After a reset is released, perform the processing according to Figure 22-9 Initial Setting of Interrupt and Reset Mode.
Page 752 RL78/G1D CHAPTER 22 VOLTAGE DETECTOR When setting an interrupt and reset mode (LVIMDS1, LVIMDS0 = 1, 0), voltage detection stabilization wait time for 400 µs or 5 clocks of f is necessary after LVD reset is released (LVIRF = 1). After waiting until voltage detection stabilizes, (0) clear the LVIMD bit for initialization.
Page 753 RL78/G1D CHAPTER 22 VOLTAGE DETECTOR 22.5 Cautions for Voltage Detector (1) In a system where the supply voltage (V ) fluctuates for a certain period in the vicinity of the LVD detection voltage, the system may be repeatedly reset and released from the reset status. In this case, the time from release of reset to the start of the operation of the microcontroller can be arbitrarily set by taking the following action.
Page 754 RL78/G1D CHAPTER 22 VOLTAGE DETECTOR (2) Delay from the time LVD reset source is generated until the time LVD reset has been generated or released There is some delay from the time supply voltage (V ) < LVD detection voltage (V ) until the time LVD reset has been generated.
Page 755 RL78/G1D CHAPTER 23 SAFETY FUNCTIONS CHAPTER 23 SAFETY FUNCTIONS 23.1 Overview of Safety Functions The following safety functions are provided in the RL78/G1D to comply with the IEC60730 and IEC61508 safety standards. These functions enable the microcontroller to self-diagnose abnormalities and stop operating if an abnormality is detected.
Page 756 RL78/G1D CHAPTER 23 SAFETY FUNCTIONS 23.2 Registers Used by Safety Functions The safety functions use the following registers for each function. Register Each Function of Safety Function ● Flash memory CRC control register (CRC0CTL) Flash memory CRC operation function ● Flash memory CRC operation result register (PGCRCL) (high-speed CRC) ●...
Page 757 RL78/G1D CHAPTER 23 SAFETY FUNCTIONS Figure 23-1. Format of Flash Memory CRC Control Register (CRC0CTL) Address: F02F0H After reset: 00H Symbol <7> CRC0CTL CRC0EN FEA5 FEA4 FEA3 FEA2 FEA1 FEA0 CRC0EN Control of CRC ALU operation Stop the operation. Start the operation according to HALT instruction execution. FEA5 FEA4 FEA3...
Page 758 RL78/G1D CHAPTER 23 SAFETY FUNCTIONS 23.3.1.2 Flash memory CRC operation result register (PGCRCL) This register is used to store the high-speed CRC operation results. The PGCRCL register can be set by a 16-bit memory manipulation instruction. Reset signal generation clears this register to 0000H. Figure 23-2.
Page 759 RL78/G1D CHAPTER 23 SAFETY FUNCTIONS <Operation flow> <R> Figure 23-3. Flowchart of Flash Memory CRC Operation Function (High-speed CRC) Start ; Store the expected CRC operation result ; value in the lowest 4 bytes. Set FEA5 to FEA0 bits ; Set CRC operation range. ;...
Page 760 RL78/G1D CHAPTER 23 SAFETY FUNCTIONS 23.3.2 CRC operation function (general-purpose CRC) In order to guarantee safety during operation, the IEC61508 standard mandates the checking of data even while the CPU is operating. In the RL78/G1D, a general CRC operation can be executed as a peripheral function while the CPU is operating. The general CRC can be used for checking various data in addition to the code flash memory area.
Page 761 RL78/G1D CHAPTER 23 SAFETY FUNCTIONS 23.3.2.2 CRC data register (CRCD) This register is used to store the CRC operation result of the general-purpose CRC. The setting range is 0000H to FFFFH. After 1 clock of CPU/peripheral hardware clock (f ) has elapsed from the time CRCIN register is written, the CRC operation result is stored to the CRCD register.
Page 762 RL78/G1D CHAPTER 23 SAFETY FUNCTIONS 23.3.3 RAM parity error detection function The IEC60730 standard mandates the checking of RAM data. A single-bit parity bit is therefore added to all 8-bit data in the RL78/G1D’s RAM. By using this RAM parity error detection function, the parity bit is appended when data is written, and the parity is checked when the data is read.
Page 763 RL78/G1D CHAPTER 23 SAFETY FUNCTIONS Figure 23-8. Flowchart of RAM Parity Check Start of check Note RPERF = 1 RPERDIS = 1 Disable parity error reset. Check RAM. Check RAM. Read RAM. RPEF = 1 Parity error Parity error generation generated? checked Enable parity...
Page 764 RL78/G1D CHAPTER 23 SAFETY FUNCTIONS 23.3.4 RAM guard function In order to guarantee safety during operation, the IEC61508 standard mandates that important data stored in the RAM be protected, even if the CPU freezes. This RAM guard function is used to protect data in the specified memory space. If the RAM guard function is specified, writing to the specified RAM space is disabled, but reading from the space can be carried out as usual.
Page 765 RL78/G1D CHAPTER 23 SAFETY FUNCTIONS 23.3.5 SFR guard function In order to guarantee safety during operation, the IEC61508 standard mandates that important SFRs be protected from being overwritten, even if the CPU freezes. This SFR guard function is used to protect data in the control registers used by the port function, interrupt function, clock control function, voltage detection function, and RAM parity error detection function.
Page 766 RL78/G1D CHAPTER 23 SAFETY FUNCTIONS 23.3.6 Invalid memory access detection function The IEC60730 standard mandates checking that the CPU and interrupts are operating correctly. The illegal memory access detection function triggers a reset if a memory space specified as access-prohibited is accessed.
Page 767 RL78/G1D CHAPTER 23 SAFETY FUNCTIONS Note The following table lists the code flash memory, RAM, and lowest detection address for each product: Products Code flash memory Detected lowest address for (00000H to xxxxxH) (zzzzzH to FFEFFH) read/instruction fetch (execution) (yyyyyH) 131072 ×...
Page 768 RL78/G1D CHAPTER 23 SAFETY FUNCTIONS 23.3.7 Frequency detection function The IEC60730 standard mandates checking that the oscillation frequency is correct. By using the CPU/peripheral hardware clock frequency (f ) and measuring the pulse width of the input signal to channel 5 of the timer array unit 0 (TAU0), whether the proportional relationship between the two clock frequencies is correct can be determined.
Page 769 RL78/G1D CHAPTER 23 SAFETY FUNCTIONS 23.3.7.1 Timer input select register 0 (TIS0) The TIS0 register is used to select the timer input of channel 5 of the timer array unit 0 (TAU0). The TIS0 register can be set by an 8-bit memory manipulation instruction. Reset signal generation clears this register to 00H.
Page 770 RL78/G1D CHAPTER 23 SAFETY FUNCTIONS 23.3.8 A/D test function The IEC60730 standard mandates testing the A/D converter. The A/D test function checks whether or not the A/D converter is operating normally by executing A/D conversions of the A/D converter’s positive and negative reference voltages, analog input channel (ANI), temperature sensor output voltage, and the internal reference voltage.
Page 771 RL78/G1D CHAPTER 23 SAFETY FUNCTIONS Figure 23-15. Configuration of A/D Test Function ADISS ADS4 to ADS0 ANI0/AV REFP ANI1/AV REFM ANIxx ADTES1, ADTES0 ANIxx Temperature Note sensor Internal reference voltage (1.45 V) Positive reference voltage of AD converter ADREFP1 A/D converter ADREFP0 Negative reference voltage of AD converter...
Page 772 RL78/G1D CHAPTER 23 SAFETY FUNCTIONS 23.3.8.1 A/D test register (ADTES) This register is used to select the A/D converter’s positive reference voltage, A/D converter’s negative reference voltage, analog input channel (ANIxx), temperature sensor output voltage, or internal reference voltage (1.45 V) as the target of A/D conversion.
Page 773 RL78/G1D CHAPTER 23 SAFETY FUNCTIONS 23.3.8.2 Analog input channel specification register (ADS) This register specifies the input channel of the analog voltage to be A/D converted. Set A/D test register (ADTES) to 00H when measuring the ANIxx/temperature sensor output voltage/internal reference voltage (1.45 V).
Page 774 RL78/G1D CHAPTER 24 REGULATOR CHAPTER 24 REGULATOR 24.1 Regulator Overview The RL78/G1D contains a circuit for operating the device with a constant voltage. At this time, in order to stabilize the regulator output voltage, connect the REGC pin to V via a capacitor (0.47 to 1 µF).
Page 775 RL78/G1D CHAPTER 25 OPTION BYTE CHAPTER 25 OPTION BYTE 25.1 Functions of Option Bytes Addresses 000C0H to 000C3H of the flash memory of the RL78/G1D form an option byte area. Option bytes consist of user option byte (000C0H to 000C2H) and on-chip debug option byte (000C3H). Upon power application or resetting and starting, an option byte is automatically referenced and a specified function is set.
Page 776 RL78/G1D CHAPTER 25 OPTION BYTE (3) 000C2H/010C2H ○ Setting of flash operation mode Make the setting depending on the main system clock frequency (f ) and power supply voltage (V ) to be MAIN used. ● LV (low voltage main) mode ●...
Page 777 RL78/G1D CHAPTER 25 OPTION BYTE 25.2 Format of User Option Byte The format of user option byte is shown below. Figure 25-1. Format of User Option Byte (000C0H/010C0H) Note 1 Address: 000C0H/010C0H WDTINIT WINDOW1 WINDOW0 WDTON WDCS2 WDCS1 WDCS0 WDSTBYON WDTINIT Use of interval interrupt of watchdog timer Interval interrupt is not used.
Page 778 RL78/G1D CHAPTER 25 OPTION BYTE <R> Note 3. When the window open period is set to 75%, clearing the counter of the watchdog timer (writing ACH to WDTE) must proceed outside the corresponding period from among those listed below, over which clearing of the counter is prohibited (for example, confirming that the interval timer interrupt request flag (WDTIIF) of the watchdog timer is set).
Page 779 RL78/G1D CHAPTER 25 OPTION BYTE Figure 25-2. Format of User Option Byte (000C1H/010C1H) (1/2) Note Address: 000C1H/010C1H VPOC2 VPOC1 VPOC0 LVIS1 LVIS0 LVIMDS1 LVIMDS0 ● LVD setting (interrupt & reset mode) Detection voltage Option byte setting value VPOC2 VPOC1 VPOC0 LVIS1 LVIS0 Mode setting...
Page 780 RL78/G1D CHAPTER 25 OPTION BYTE Figure 25-2. Format of User Option Byte (000C1H/010C1H) (2/2) Note Address: 000C1H/010C1H VPOC2 VPOC1 VPOC0 LVIS1 LVIS0 LVIMDS1 LVIMDS0 ● LVD setting (interrupt mode) Detection voltage Option byte setting value VPOC2 VPOC1 VPOC0 LVIS1 LVIS0 Mode setting Rising edge Falling edge...
Page 781 RL78/G1D CHAPTER 25 OPTION BYTE Figure 25-3. Format of Option Byte (000C2H/010C2H) Note Address: 000C2H/010C2H CMODE1 CMODE0 FRQSEL3 FRQSEL2 FRQSEL1 FRQSEL0 CMODE1 CMODE0 Setting of flash operation mode Operating Operating Voltage Frequency Range (f Range (V MAIN LV (low voltage main) mode 1 to 4 MHz 1.6 to 3.6 V LS (low speed main) mode...
Page 782 RL78/G1D CHAPTER 25 OPTION BYTE 25.3 Format of On-chip Debug Option Byte The format of on-chip debug option byte is shown below. Figure 25-4. Format of On-chip Debug Option Byte (000C3H/010C3H) Note Address: 000C3H/010C3H OCDENSET OCDERSD OCDENSET OCDERSD Control of on-chip debug operation Disables on-chip debug operation.
Page 783 RL78/G1D CHAPTER 25 OPTION BYTE 25.4 Setting of Option Byte The user option byte and on-chip debug option byte can be set using the link option, in addition to describing to the source. When doing so, the contents set by using the link option take precedence, even if descriptions exist in the source, as mentioned below.
Page 784 RL78/G1D CHAPTER 26 FLASH MEMORY CHAPTER 26 FLASH MEMORY The RL78/G1D incorporates the flash memory to which a program can be written, erased, and overwritten. The flash memory includes the “code flash memory”, in which programs can be executed, and the “data flash memory”, an area for storing data.
Page 785 RL78/G1D CHAPTER 26 FLASH MEMORY The following methods for programming the flash memory are available. The code flash memory can be rewritten to through serial programming using a flash memory programmer or an external device (UART communication), or through self-programming. ●...
Page 786 RL78/G1D CHAPTER 26 FLASH MEMORY 26.1 Serial Programming Using Flash Memory Programmer The following dedicated flash memory programmer can be used to write data to the internal flash memory of the RL78 microcontroller. ● PG-FP5, FL-PR5 ● E1 on-chip debugging emulator Data can be written to the flash memory on-board or off-board, by using a dedicated flash memory programmer.
Page 787 RL78/G1D CHAPTER 26 FLASH MEMORY 26.1.1 Programming environment The environment required for writing a program to the flash memory of the RL78 microcontroller is illustrated below. Figure 26-1. Environment for Writing Program to Flash Memory PG-FP5, FL-PR5 RS-232C RESET RL78 Dedicated flash TOOL0 (dedicated single-line UART) microcontroller...
Page 788 RL78/G1D CHAPTER 26 FLASH MEMORY The dedicated flash memory programmer generates the following signals for the RL78 microcontroller. See each manual of PG-FP5, FL-PR5, or E1 on-chip debugging emulator for details. Table 26-2. Pin Connection Dedicated Flash Memory Programmer RL78 Microcontroller Signal Name Pin Function Pin Name...
Page 789 RL78/G1D CHAPTER 26 FLASH MEMORY 26.2.2 Communication mode Communication between the external device and the RL78 microcontroller is established by serial communication using the TOOLTxD and TOOLRxD pins via the dedicated UART of the RL78 microcontroller. Transfer rate: 1 M, 500 k, 250 k, 115.2kbps Figure 26-4.
Page 790 RL78/G1D CHAPTER 26 FLASH MEMORY 26.3 Connection of Pins on Board To write the flash memory on-board by using the flash memory programmer, connectors that connect the dedicated flash memory programmer must be provided on the target system. First provide a function that selects the normal operation mode or flash memory programming mode on the board.
Page 791 RL78/G1D CHAPTER 26 FLASH MEMORY 26.3.3 Port pins When the flash memory programming mode is set, all the pins not used for flash memory programming enter the same status as that immediately after reset. If external devices connected to the ports do not recognize the port status immediately after reset, the port pin must be connected to V or to V via a resistor.
Page 792 RL78/G1D CHAPTER 26 FLASH MEMORY 26.4 Serial Programming Method 26.4.1 Serial programming procedure The following figure illustrates a flow for rewriting the code flash memory through serial programming. Figure 26-6. Code Flash Memory Manipulation Procedure Start Flash memory programming Controlling TOOL0 pin and RESET pin mode is set Manipulate code flash memory End?
Page 793 RL78/G1D CHAPTER 26 FLASH MEMORY 26.4.2 Flash memory programming mode To rewrite the contents of the code flash memory through serial programming, set the RL78 microcontroller to the flash memory programming mode. To enter the mode, set as follows. <Serial programming using the dedicated flash memory programmer> Connect the RL78 microcontroller to a dedicated flash memory programmer.
Page 794 RL78/G1D CHAPTER 26 FLASH MEMORY There are two flash memory programming modes: wide voltage mode and full speed mode. The supply voltage value applied to the microcontroller during write operations and the setting information of the user option byte for setting of the flash memory programming mode determine which mode is selected.
Page 795 RL78/G1D CHAPTER 26 FLASH MEMORY 26.4.3 Selecting communication mode Communication modes of the RL78 microcontroller are as follows. Table 26-6. Communication Modes Note 1 Communication Standard Setting Pins Used Mode Note 2 Port Speed Frequency Multiply Rate 1-line UART UART 115200 bps, TOOL0 –...
Page 796 RL78/G1D CHAPTER 26 FLASH MEMORY Product information (such as product name and firmware version) can be obtained by executing the “Silicon Signature” command. Table 26-8 is a list of signature data and Table 26-9 shows an example of signature data. Table 26-8.
Page 797 RL78/G1D CHAPTER 26 FLASH MEMORY 26.5 Processing Time for Each Command When PG-FP5 Is in Use (Reference Value) The following shows the processing time for each command (reference value) when PG-FP5 is used as a dedicated flash memory programmer. Table 26-10. Processing Time for Each Command When PG-FP5 Is in Use (Reference Value) PG-FP5 Command Code Flash 128 Kbytes...
Page 798 LS (low speed main) mode or LV (low voltage main) mode is specified. If the argument fsl_flash_voltage_u08 is 00H when the FSL_Init function of the flash self-programming library provided by Renesas Electronics is executed, full speed mode is specified. If the argument is other than 00H, the wide voltage mode is specified.
Page 799 RL78/G1D CHAPTER 26 FLASH MEMORY 26.6.1 Self-programming procedure The following figure illustrates a flow for rewriting the code flash memory by using a flash self-programming library. Figure 26-8. Flow of Self Programming (Rewriting Flash Memory) Code flash memory control start Initialize flash environment Flash shield window setting Erase...
Page 800 RL78/G1D CHAPTER 26 FLASH MEMORY 26.6.2 Boot swap function If rewriting the boot area failed by temporary power failure or other reasons, restarting a program by resetting or overwriting is disabled due to data destruction in the boot area. The boot swap function is used to avoid this problem. Note Before erasing boot cluster 0 , which is a boot area, by self-programming, write a new boot program to boot cluster 1...
Page 801 RL78/G1D CHAPTER 26 FLASH MEMORY Figure 26-10. Example of Executing Boot Swapping Block number Erasing block 4 Erasing block 5 Erasing block 6 Erasing block 7 User program User program User program User program User program User program User program Boot User program User program...
Page 802 RL78/G1D CHAPTER 26 FLASH MEMORY 26.6.3 Flash shield window function The flash shield window function is provided as one of the security functions for self-programming. It disables writing to and erasing areas outside the range specified as a window only during self-programming. The window range can be set by specifying the start and end blocks.
Page 803 RL78/G1D CHAPTER 26 FLASH MEMORY 26.7 Security Settings The RL78 microcontroller supports a security function that prohibits rewriting the user program written to the internal flash memory, so that the program cannot be changed by an unauthorized person. The operations shown below can be performed using the Security Set command. ●...
Page 804 RL78/G1D CHAPTER 26 FLASH MEMORY Table 26-12. Relationship Between Enabling Security Function and Command (1) During serial programming Valid Security Executed Command Block Erase Write Note Prohibition of block erase Blocks cannot be erased. Can be performed. Prohibition of writing Blocks can be erased.
Page 805 RL78/G1D CHAPTER 26 FLASH MEMORY 26.8 Data Flash 26.8.1 Data flash overview An overview of the data flash memory is provided below. ● The user program can rewrite the data flash memory by using the data flash library. For details, refer to RL78 Family Data Flash Library User’s Manual.
Page 806 RL78/G1D CHAPTER 26 FLASH MEMORY 26.8.2 Register controlling data flash memory (1) Data flash control register (DFLCTL) This register is used to enable or disable accessing to the data flash. The DFLCTL register is set by a 1-bit or 8-bit memory manipulation instruction. Reset input sets this register to 00H.
Page 807 RL78/G1D CHAPTER 26 FLASH MEMORY 26.8.3 Procedure for accessing data flash memory The data flash memory is stopped after a reset ends. To access the data flash, make initial settings according to the following procedure. <1> Set bit 0 (DFLEN) of the data flash control register (DFLCTL) to 1. <2>...
Page 808 Renesas Electronics is not liable for problems occurring when the on-chip debug function is used.
Page 809 To perform communication between the RL78 microcontroller and E1 on-chip debugging emulator, as well as each debug function, the securing of memory space must be done beforehand. If Renesas Electronics assembler or compiler is used, the items can be set by using link options. (1) Securement of memory space The shaded portions in Figure 27-2 are the areas reserved for placing the debug monitor program, so user programs or data cannot be allocated in these spaces.
Page 810 RL78/G1D CHAPTER 27 ON-CHIP DEBUG FUNCTION Figure 27-2. Memory Spaces Where Debug Monitor Programs Are Allocated Code flash memory Internal RAM Use prohibited SFR area Note 1 (512 bytes or Note 2 256 bytes Stack area for debugging Internal RAM Note 4 (4 bytes) area...
Page 811 RL78/G1D CHAPTER 28 BCD CORRECTION CIRCUIT CHAPTER 28 BCD CORRECTION CIRCUIT 28.1 BCD Correction Circuit Function The result of addition/subtraction of the BCD (binary-coded decimal) code and BCD code can be obtained as BCD code with this circuit. The decimal correction operation result is obtained by performing addition/subtraction having the A register as the operand and then adding/ subtracting the BCD correction result register (BCDADJ).
Page 812 RL78/G1D CHAPTER 28 BCD CORRECTION CIRCUIT 28.3 BCD Correction Circuit Operation The basic operation of the BCD correction circuit is as follows. (1) Addition: Calculating the result of adding a BCD code value and another BCD code value by using a BCD code value <1>...
Page 813 RL78/G1D CHAPTER 28 BCD CORRECTION CIRCUIT (2) Subtraction: Calculating the result of subtracting a BCD code value from another BCD code value by using a BCD code value <1> The BCD code value from which subtraction is performed is stored in the A register. <2>...
Page 814 RL78/G1D CHAPTER 29 INSTRUCTION SET CHAPTER 29 INSTRUCTION SET This chapter lists the instructions in the RL78 microcontroller instruction set. For details of each operation and operation code, refer to the separate document RL78 Microcontrollers User’s Manual: software (R01US0015). 29.1 Conventions Used in Operation List 29.1.1 Operand identifiers and specification methods Operands are described in the “Operand”...
Page 815 RL78/G1D CHAPTER 29 INSTRUCTION SET 29.1.2 Description of operation column The operation when the instruction is executed is shown in the “Operation” column using the following symbols. Table 29-2. Symbols in “Operation” Column Symbol Function A register; 8-bit accumulator X register B register C register D register...
Page 816 RL78/G1D CHAPTER 29 INSTRUCTION SET 29.1.3 Description of flag operation column The change of the flag value when the instruction is executed is shown in the “Flag” column using the following symbols. Table 29-3. Symbols in “Flag” Column Symbol Change of Flag Value (Blank) Unchanged Cleared to 0...
Page 817 RL78/G1D CHAPTER 29 INSTRUCTION SET 29.2 Operation List Table 29-5. Operation List (1/17) Instruction Mnemonic Operands Bytes Clocks Operation Flag Group Note 1 Note 2 AC CY 8-bit data r, #byte – r ← byte transfer × × × PSW, #byte –...
Page 818 RL78/G1D CHAPTER 29 INSTRUCTION SET Table 29-5. Operation List (2/17) Instruction Mnemonic Operands Bytes Clocks Operation Flag Group Note 1 Note 2 AC CY 8-bit data A, sfr – A ← sfr transfer sfr, A – sfr ← A A, [DE] A ←...
Page 819 RL78/G1D CHAPTER 29 INSTRUCTION SET Table 29-5. Operation List (3/17) Instruction Mnemonic Operands Bytes Clocks Operation Flag Group Note 1 Note 2 AC CY 8-bit data A, [HL+B] A ← (HL + B) transfer [HL+B], A – (HL + B) ← A A, ES:[HL+B] A ←...
Page 820 RL78/G1D CHAPTER 29 INSTRUCTION SET Table 29-5. Operation List (4/17) Instruction Mnemonic Operands Bytes Clocks Operation Flag Group Note 1 Note 2 AC CY 8-bit data A, [HL+B] – A ←→ (HL+B) transfer A, ES:[HL+B] – A ←→ ((ES, HL)+B) A, [HL+C] –...
Page 821 RL78/G1D CHAPTER 29 INSTRUCTION SET Table 29-5. Operation List (5/17) Instruction Mnemonic Operands Bytes Clocks Operation Flag Group Note 1 Note 2 AC CY 16-bit MOVW AX, [DE] AX ← (DE) data [DE], AX – (DE) ← AX transfer AX, ES:[DE] AX ←...
Page 822 RL78/G1D CHAPTER 29 INSTRUCTION SET Table 29-5. Operation List (6/17) Instruction Mnemonic Operands Bytes Clocks Operation Flag Group Note 1 Note 2 AC CY 16-bit MOVW BC, !addr16 BC ← (addr16) data BC, ES:!addr16 BC ← (ES, addr16) transfer DE, !addr16 DE ←...
Page 823 RL78/G1D CHAPTER 29 INSTRUCTION SET Table 29-5. Operation List (7/17) Instruction Mnemonic Operands Bytes Clocks Operation Flag Group Note 1 Note 2 AC CY 8-bit ADDC A, #byte – A, CY ← A+byte+CY × × × operation saddr, #byte – (saddr), CY ←...
Page 824 RL78/G1D CHAPTER 29 INSTRUCTION SET Table 29-5. Operation List (8/17) Instruction Mnemonic Operands Bytes Clocks Operation Flag Group Note 1 Note 2 AC CY 8-bit SUBC A, #byte – A, CY ← A – byte – CY × × × operation saddr, #byte –...
Page 825 RL78/G1D CHAPTER 29 INSTRUCTION SET Table 29-5. Operation List (9/17) Instruction Mnemonic Operands Bytes Clocks Operation Flag Group Note 1 Note 2 AC CY A ← Abyte × 8-bit A, #byte – operation (saddr) ← (saddr)byte × saddr, #byte – Note 3 A ←...
Page 826 RL78/G1D CHAPTER 29 INSTRUCTION SET Table 29-5. Operation List (10/17) Instruction Mnemonic Operands Bytes Clocks Operation Flag Group Note 1 Note 2 AC CY 8-bit A, #byte – A – byte × × × operation !addr16, #byte (addr16) – byte ×...
Page 827 RL78/G1D CHAPTER 29 INSTRUCTION SET Table 29-5. Operation List (11/17) Instruction Mnemonic Operands Bytes Clocks Operation Flag Group Note 1 Note 2 AC CY 16-bit ADDW AX, #word – AX, CY ← AX+word × × × operation AX, AX – AX, CY ←...
Page 828 RL78/G1D CHAPTER 29 INSTRUCTION SET Table 29-5. Operation List (12/17) Instruction Mnemonic Operands Bytes Clocks Operation Flag Group Note 1 Note 2 AC CY Increment/ – r ← r+1 × × decrement !addr16 – (addr16) ← (addr16)+1 × × ES:!addr16 –...
Page 829 RL78/G1D CHAPTER 29 INSTRUCTION SET Table 29-5. Operation List (13/17) Instruction Mnemonic Operands Bytes Clocks Operation Flag Group Note 1 Note 2 AC CY Rotate A, 1 – (CY, A ← A ← A )×1 × A, 1 – (CY, A ←...
Page 830 RL78/G1D CHAPTER 29 INSTRUCTION SET Table 29-5. Operation List (14/17) Instruction Mnemonic Operands Bytes Clocks Operation Flag Group Note 1 Note 2 AC CY CY ← CY ⊻ A.bit XOR1 CY, A.bit – × manipulate CY ← CY ⊻ (saddr).bit CY, saddr.bit –...
Page 831 RL78/G1D CHAPTER 29 INSTRUCTION SET Table 29-5. Operation List (15/17) Instruction Mnemonic Operands Bytes Clocks Operation Flag Group Note 1 Note 2 AC CY Call/ CALL – (SP – 2) ← (PC+2) , (SP – 3) ← (PC+2) return (SP – 4) ← (PC+2) , PC ←...
Page 832 RL78/G1D CHAPTER 29 INSTRUCTION SET Table 29-5. Operation List (16/17) Instruction Mnemon Operands Bytes Clocks Operation Flag Group Note 1 Note 2 AC CY Stack PUSH – (SP – 1) ← PSW, (SP – 2) ← 00H manipulate – (SP – 1) ← rp , (SP –...
Page 833 RL78/G1D CHAPTER 29 INSTRUCTION SET Table 29-5. Operation List (17/17) Instruction Mnemonic Operands Bytes Clocks Operation Flag Group Note 1 Note 2 AC CY Note3 Condition saddr.bit, $addr20 – PC ← PC + 4 + jdisp8 if (saddr).bit = 0 al branch Note3 sfr.bit, $addr20...
Page 834 Renesas Electronics is not liable for problems occurring when the on-chip debug function is used. R01UH0515EJ0120 Rev.1.20...
Page 835 RL78/G1D CHAPTER 30 ELECTRICAL SPECIFICATIONS 30.1 Absolute Maximum Ratings °C Absolute Maximum Ratings (T = 25 ) (1/2) Parameter Symbols Conditions Ratings Unit Supply voltage –0.5 to +6.5 –0.5 to +4.0 DDRF1 DD_RF –0.5 to +4.0 DDRF2 DD_RF DCLIN –0.5 to +4.0 DDRF3 , AV –0.5 to +0.3...
Page 836 RL78/G1D CHAPTER 30 ELECTRICAL SPECIFICATIONS Absolute Maximum Ratings (T = 25°C) (2/2) Parameter Symbols Conditions Ratings Unit Output current, Per pin (This is applicable to all pins listed below.) –40 high Total of all pins P00, P01, P02, P03, P40, P120, P130, P140 –70 –170mA P10, P11, P12, P13, P14, P15, P16, P30, P147...
Page 837 RL78/G1D CHAPTER 30 ELECTRICAL SPECIFICATIONS 30.2 Operating Voltage – 40 to +85°C, V = AV = AV = 0 V) DD_RF DD _RF SS_RF SS_RF Flash operation mode Clock generator Operation voltage CPU operation clocks Note 1 Main system clock High-speed on-chip oscillator HS (high-speed main) mode 2.7 V ≤...
Page 838 RL78/G1D CHAPTER 30 ELECTRICAL SPECIFICATIONS 30.3 Oscillator Characteristics 30.3.1 X1, XT1, XRF oscillator characteristics – 40 to +85°C, 1.6 V ≤ V = AV ≤ 3.6 V, V = AV = 0 V) DD_RF DD_RF SS_RF SS_RF Parameter Symbol Conditions MIN.
Page 839 RL78/G1D CHAPTER 30 ELECTRICAL SPECIFICATIONS 30.3.2 On-chip oscillator characteristics – 40 to +85°C, 1.6 V ≤ V = AV ≤ 3.6 V, V = AV = 0 V) DD_RF DD_RF SS_RF SS_RF Oscillators Symbol Conditions MIN. TYP. MAX. Unit High-speed on-chip oscillator clock Notes 1, 2 frequency 1.8 V ≤...
Page 840 RL78/G1D CHAPTER 30 ELECTRICAL SPECIFICATIONS 30.4 DC Characteristics 30.4.1 Output current = –40 to +85°C, 1.6 V ≤ V = AV ≤ 3.6 V, V = AV = 0 V) DD_RF DD_RF SS_RF SS_RF Items Symbol Conditions MIN. TYP. MAX. Unit Note 2 Output current,...
Page 841 RL78/G1D CHAPTER 30 ELECTRICAL SPECIFICATIONS Caution P00, P02, P03, and P10 to P15 do not output high level in N-ch open-drain mode. Remark Unless specified otherwise, the characteristics of alternate-function pins are the same as those of the port pins. 30.4.2 Input current = –40 to +85°C, 1.6 V ≤...
Page 842 RL78/G1D CHAPTER 30 ELECTRICAL SPECIFICATIONS 30.4.3 Output voltage = –40 to +85°C, 1.6 V ≤ V = AV ≤ 3.6 V, V = AV = 0 V) DD_RF DD_RF SS_RF SS_RF Items Symbol Conditions MIN. TYP. MAX. Unit Output = –2.0 mA P00, P01, P02, P03, P10, 2.7 V ≤...
Page 843 RL78/G1D CHAPTER 30 ELECTRICAL SPECIFICATIONS 30.4.4 Input leakage current = –40 to +85°C, 1.6 V ≤ V = AV ≤ 3.6 V, V = AV = 0 V) DD_RF DD_RF SS_RF SS_RF Items Symbol Conditions MIN. TYP. MAX. Unit Input leakage current, VI = V P00, P01, P02, P03, P10, P11, P12, P13, P14, µA...
Page 844 RL78/G1D CHAPTER 30 ELECTRICAL SPECIFICATIONS 30.5 Current Consumption The Current Consumption by the RL78/G1D is the total current including that for the MCU (current flowing into the V pin) and that for the RF unit (current flowing into the V pins).
Page 845 RL78/G1D CHAPTER 30 ELECTRICAL SPECIFICATIONS Notes 1. Current flowing into V , including the input leakage current flowing when the level of the input pin is fixed to or V . The values below the MAX. column include the peripheral operation current. However, not including the current flowing into the A/D converter, LVD circuit, I/O port, and on-chip pull-up/pull-down resistors and the current flowing during data flash rewrite.
Page 846 RL78/G1D CHAPTER 30 ELECTRICAL SPECIFICATIONS (2) Standby current = –40 to +85°C, 1.6 V ≤ V = AV ≤ 3.6 V, V = AV = 0 V) DD_RF DD_RF SS_RF SS_RF Parameter Symbol Conditions MIN. TYP. MAX. Unit Note 4 HALT HS (high-speed = 32 MHz...
Page 847 RL78/G1D CHAPTER 30 ELECTRICAL SPECIFICATIONS Notes 1. Current flowing into V , including the input leakage current flowing when the level of the input pin is fixed to or V . The values below the MAX. column include the peripheral operation current. However, not including the current flowing into the A/D converter, LVD circuit, I/O port, and on-chip pull-up/pull-down resistors and the current flowing during data flash rewrite.
Page 848 RL78/G1D CHAPTER 30 ELECTRICAL SPECIFICATIONS (3) Current for each peripheral circuit = –40 to +85°C, 1.6 V ≤ V = AV ≤ 3.6 V, V = AV = 0 V) DD_RF DD_RF SS_RF SS_RF Parameter Symbol Conditions MIN. TYP. MAX. Unit Note 1 Low-speed on-chip oscillator 0.20...
Page 849 RL78/G1D CHAPTER 30 ELECTRICAL SPECIFICATIONS Remarks 1. f Low-speed on-chip oscillator clock frequency 2. f : Subsystem clock frequency 3. f : CPU and peripheral hardware clock frequency 4. Temperature condition of the TYP. value is T = 25°C 30.5.2 RF unit = –40 to +85°C, 1.6 V ≤...
Page 850 RL78/G1D CHAPTER 30 ELECTRICAL SPECIFICATIONS 30.6 AC Characteristics = –40 to +85°C, 1.6 V ≤ V = AV ≤ 3.6 V, V = AV = 0 V) DD_RF DD_RF SS_RF SS_RF Items Symbol Conditions MIN. TYP. MAX. Unit Cycle time (minimum instruction Main system HS (high-speed 2.7 V ≤...
Page 851 RL78/G1D CHAPTER 30 ELECTRICAL SPECIFICATIONS = –40 to +85°C, 1.6 V ≤ V = AV ≤ 3.6 V, V = AV = 0 V) (2/2) DD_RF DD_RF SS_RF SS_RF Items Symbol Conditions MIN. TYP. MAX. Unit Interrupt input high-level width, INTP0, INTP3, INTP5, INTP6 µs INTH,...
Page 852 RL78/G1D CHAPTER 30 ELECTRICAL SPECIFICATIONS vs V (LS (low-speed main) mode) When the high-speed on-chip oscillator clock is selected During self programming When high-speed system clock is selected 0.125 0.01 Supply voltage V vs V (LV (low-voltage main) mode) When the high-speed on-chip oscillator clock is selected During self programming When high-speed system clock is selected 0.01...
Page 853 RL78/G1D CHAPTER 30 ELECTRICAL SPECIFICATIONS AC Timing Test Points Test points External System Clock Timing EXLS EXHS EXCLK/EXCLKS TI/TO Timing TI00 to TI07, TI10 to TI17 TO00 to TO07, TO10 to TO17 Interrupt Request Input Timing INTL INTH INTP0, INTP3, INTP5, INTP6 RESET Input Timing RESET R01UH0515EJ0120 Rev.1.20...
Page 854 RL78/G1D CHAPTER 30 ELECTRICAL SPECIFICATIONS 30.7 Peripheral Functions Characteristics AC Timing Test Points Test points 30.7.1 Serial array unit (1) During communication at same potential (UART mode) = –40 to +85°C, 1.6 V ≤ V = AV ≤ 3.6 V, V = AV = 0 V) DD_RF...
Page 855 RL78/G1D CHAPTER 30 ELECTRICAL SPECIFICATIONS UART mode connection diagram (during communication at same potential) TxDq RL78 microcontroller User device RxDq UART mode bit width (during communication at same potential) (reference) 1/Transfer rate High-/Low-bit width Baud rate error tolerance TxDq RxDq Remarks 1.
Page 856 RL78/G1D CHAPTER 30 ELECTRICAL SPECIFICATIONS (2) During communication at same potential (CSI mode) (master mode, SCKp... internal clock output, supporting CSI00 only) = –40 to +85°C, 2.7 V ≤ V = AV ≤ 3.6 V, V = AV = 0 V) DD_RF DD_RF SS_RF...
Page 857 RL78/G1D CHAPTER 30 ELECTRICAL SPECIFICATIONS (3) During communication at same potential (CSI mode) (Internal communication, supporting CSI21 only) = –40 to +85°C, 1.6 V ≤ V = AV ≤ 3.6 V, V = AV = 0 V) DD_RF DD_RF SS_RF SS_RF Parameter Symbol...
Page 858 RL78/G1D CHAPTER 30 ELECTRICAL SPECIFICATIONS (4) During communication at same potential (CSI mode) (master mode, SCKp... internal clock output, supporting CSI00 and CSI20) = –40 to +85°C, 1.6 V ≤ V = AV ≤ 3.6 V, V = AV = 0 V) DD_RF DD_RF SS_RF...
Page 859 RL78/G1D CHAPTER 30 ELECTRICAL SPECIFICATIONS (5) During communication at same potential (CSI mode) (slave mode, SCKp... external clock input, supporting CSI00 and CSI20) = –40 to +85°C, 1.6 V ≤ V = AV ≤ 3.6 V, V = AV = 0 V) DD_RF DD_RF SS_RF...
Page 860 RL78/G1D CHAPTER 30 ELECTRICAL SPECIFICATIONS Caution Select the normal input buffer for the SIp pin and SCKp pin and the normal output mode for the SOp pin by using port input mode register g (PIMg) and port output mode register g (POMg). Remarks 1.
Page 861 RL78/G1D CHAPTER 30 ELECTRICAL SPECIFICATIONS CSI mode serial transfer timing (during communication at same potential) (When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1.) KCY1, 2 KL1, 2 KH1, 2 SCKp SIK1, 2 KSI1, 2 Input data KSO1, 2...
Page 862 RL78/G1D CHAPTER 30 ELECTRICAL SPECIFICATIONS (6) During communication at same potential (simplified I C mode) (1/2) = –40 to +85°C, 1.6 V ≤ V = AV ≤ 3.6 V, V = AV = 0 V) DD_RF DD_RF SS_RF SS_RF Parameter Symbol Conditions HS (high-speed...
Page 863 RL78/G1D CHAPTER 30 ELECTRICAL SPECIFICATIONS (6) During communication at same potential (simplified I C mode) (2/2) = –40 to +85°C, 1.6 V ≤ V = AV ≤ 3.6 V, V = AV = 0 V) DD_RF DD_RF SS_RF SS_RF Parameter Symbol Conditions HS (high-speed...
Page 864 RL78/G1D CHAPTER 30 ELECTRICAL SPECIFICATIONS Simplified I C mode mode connection diagram (during communication at same potential) SDAr RL78 microcontroller User device SCLr Simplified I C mode serial transfer timing (during communication at same potential) HIGH SCLr SDAr HD:DAT SU:DAT Remarks 1.
Page 865 RL78/G1D CHAPTER 30 ELECTRICAL SPECIFICATIONS (7) Communication at different potential (1.8 V, 2.5 V) (UART mode) = –40 to +85°C, 2.4 V ≤ V = AV ≤ 3.6 V, V = AV = 0 V) DD_RF DD_RF SS_RF SS_RF Parameter Symbol Conditions HS (high-speed...
Page 866 RL78/G1D CHAPTER 30 ELECTRICAL SPECIFICATIONS Maximum transfer rate = 1/{-Cb × Rb × ln (1 - 1.5/Vb)} × 3 [bps] Baud rate error (theoretical value) = (1/transfer rate × 2 - {-Cb × Rb × ln (1 - 1.5/Vb)} / (1/transfer rate) × number of transferred bits) Note 7.
Page 867 RL78/G1D CHAPTER 30 ELECTRICAL SPECIFICATIONS (8) Communication at different potential (2.5 V) (CSI mode) (master mode: SCKp... internal clock output, supporting CSI00 only) = –40 to +85°C, 2.7 V ≤ V = AV ≤ 3.6 V, V = AV = 0 V) DD_RF DD_RF SS_RF...
Page 868 RL78/G1D CHAPTER 30 ELECTRICAL SPECIFICATIONS (9) Communication at different potential (1.8 V, 2.5 V) (CSI mode: master mode, SCKp... internal clock output) = –40 to +85°C, 1.8 V ≤ V = AV ≤ 3.6 V, V = AV = 0 V) (1/2) DD_RF DD_RF...
Page 869 RL78/G1D CHAPTER 30 ELECTRICAL SPECIFICATIONS = –40 to +85°C, 1.8 V ≤ V = AV ≤ 3.6 V, V = AV = 0 V) (2/2) DD_RF DD_RF SS_RF SS_RF Parameter Symbol Conditions HS (high-speed LS (low-speed main) LV (low-voltage Unit main) Mode Mode main) Mode...
Page 870 RL78/G1D CHAPTER 30 ELECTRICAL SPECIFICATIONS CSI mode connection diagram (during communication at different potential) <Master> SCKp RL78 User's device microcontroller Remarks 1. R [Ω]:Communication line (SCKp, SOp) pull-up resistance, C [F]: Communication line (SCKp, SOp) load capacitance, V [V]: Communication line voltage 2.
Page 871 RL78/G1D CHAPTER 30 ELECTRICAL SPECIFICATIONS CSI mode serial transfer timing (master mode) (during communication at different potential) (When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1.) KCY1 SCKp SIK1 KSI1 Input data KSO1 Output data CSI mode serial transfer timing (master mode) (during communication at different potential) (When DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0.)
Page 872 RL78/G1D CHAPTER 30 ELECTRICAL SPECIFICATIONS (10) Communication at different potential (1.8 V, 2.5 V) (CSI mode) (slave mode, SCKp... external clock input) = –40 to +85°C, 1.8 V ≤ V = AV ≤ 3.6 V, V = AV = 0 V) (1/2) DD_RF DD_RF...
Page 873 RL78/G1D CHAPTER 30 ELECTRICAL SPECIFICATIONS = –40 to +85°C, 1.8 V ≤ V = AV ≤ 3.6 V, V = AV = 0 V) (2/2) DD_RF DD_RF SS_RF SS_RF Parameter Symbol Conditions HS (high-speed LS (low-speed main) LV (low-voltage Unit main) Mode Mode main) Mode...
Page 874 RL78/G1D CHAPTER 30 ELECTRICAL SPECIFICATIONS CSI mode connection diagram (during communication at different potential) <Slave> SCKp RL78 User device microcontroller Remarks 1. R [Ω]:Communication line (SOp) pull-up resistance, C [F]: Communication line (SOp) load capacitance, [V]: Communication line voltage 2. p: CSI number (p = 00, 20), m: Unit number, n: Channel number (mn = 00, 10), g: PIM and POM number (g = 0, 1) 3.
Page 875 RL78/G1D CHAPTER 30 ELECTRICAL SPECIFICATIONS CSI mode serial transfer timing (slave mode) (during communication at different potential) (When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1.) KCY2 SCKp SIK2 KSI2 Input data KSO2 Output data CSI mode serial transfer timing (slave mode) (during communication at different potential) (When DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0.)
Page 876 RL78/G1D CHAPTER 30 ELECTRICAL SPECIFICATIONS (11) Communication at different potential (1.8 V, 2.5 V) (simplified I C mode) = –40 to +85°C, 1.8 V ≤ V = AV ≤ 3.6 V, V = AV = 0 V) (1/2) DD_RF DD_RF SS_RF SS_RF Parameter...
Page 877 RL78/G1D CHAPTER 30 ELECTRICAL SPECIFICATIONS = –40 to +85°C, 1.8 V ≤ V = AV ≤ 3.6 V, V = AV = 0 V) (2/2) DD_RF DD_RF SS_RF SS_RF Parameter Symbol Conditions HS (high-speed LS (low-speed LV (low-voltage Unit main) Mode main) Mode main) Mode MIN.
Page 878 RL78/G1D CHAPTER 30 ELECTRICAL SPECIFICATIONS Simplified I C mode connection diagram (during communication at different potential) SDAr RL78 User device microcontroller SCLr Simplified I C mode serial transfer timing (during communication at different potential) HIGH SCLr SDAr HD:DAT SU:DAT Remarks 1. R [Ω]:Communication line (SDAr, SCLr) pull-up resistance, C [F]: Communication line (SDAr, SCLr) load capacitance, V...
Page 879 RL78/G1D CHAPTER 30 ELECTRICAL SPECIFICATIONS 30.7.2 Serial interface IICA (1) I C standard mode = –40 to +85°C, 1.6 V ≤ V = AV ≤ 3.6 V, V = AV = 0 V) DD_RF DD_RF SS_RF SS_RF Parameter Symbol Conditions HS (high-speed LS (low-speed LV (low-voltage...
Page 880 RL78/G1D CHAPTER 30 ELECTRICAL SPECIFICATIONS Notes 1. The first clock pulse is generated after this period when the start/restart condition is detected. The maximum value (MAX.) of t is during normal transfer and a wait state is inserted in the ACK HD:DAT (acknowledge) timing.
Page 881 RL78/G1D CHAPTER 30 ELECTRICAL SPECIFICATIONS (2) I C fast mode = –40 to +85°C, 1.8 V ≤ V = AV ≤ 3.6 V, V = AV = 0 V) DD_RF DD_RF SS_RF SS_RF Parameter Symbol Conditions HS (high-speed LS (low-speed LV (low-voltage Unit main) Mode...
Page 882 RL78/G1D CHAPTER 30 ELECTRICAL SPECIFICATIONS (3) I C fast mode plus = –40 to +85°C, 2.7 V ≤ V = AV ≤ 3.6 V, V = AV = 0 V) DD_RF DD_RF SS_RF SS_RF Parameter Symbol Conditions HS (high-speed LS (low-speed LV (low-voltage Unit main) Mode...
Page 883 RL78/G1D CHAPTER 30 ELECTRICAL SPECIFICATIONS 30.8 Analog Characteristics 30.8.1 A/D converter characteristics A/D convertor characteristics category Reference voltage Ref. voltage(+) = AV Ref. voltage(+) = V Ref. voltage(+) = V REFP Ref. voltage(–) = AV Ref. voltage(–) = V Ref. voltage(–) = AV REFM REFM Input channel...
Page 884 RL78/G1D CHAPTER 30 ELECTRICAL SPECIFICATIONS (2) When reference voltage = AV /ANI0 (ADREFP1 = 0, ADREFP0 = 1), reference voltage = AV /ANI1 REFP (–) REFM (ADREFM = 1), conversion target : ANI16 to ANI19 = –40 to +85°C, 1.6 V ≤ AV ≤...
Page 885 RL78/G1D CHAPTER 30 ELECTRICAL SPECIFICATIONS (3) When reference voltage (ADREFP1 = 0, ADREFP0 = 0), reference voltage (ADREFM = 0), (–) conversion target : ANI0 to ANI3, ANI16 to ANI19, Internal reference voltage, Temperature sensor output voltage = –40 to +85°C, 1.8 V ≤ V = AV ≤...
Page 886 RL78/G1D CHAPTER 30 ELECTRICAL SPECIFICATIONS (4) When reference voltage = Internal reference voltage (ADREFP1 = 1, ADREFP0 = 0), reference voltage (–) /ANI1 (ADREFM = 1), conversion target : ANI0 to ANI3, ANI16 to ANI19 REFM = –40 to +85°C, 2.4 V ≤ V = AV ≤...
Page 887 RL78/G1D CHAPTER 30 ELECTRICAL SPECIFICATIONS 30.8.2 Temperature sensor and internal reference voltage characteristics = –40 to +85°C, 2.4 V ≤ V = AV ≤ 3.6 V, V = AV = 0 V, HS (high-speed main) mode) DD_RF DD_RF SS_RF SS_RF Parameter Symbol Conditions...
Page 888 RL78/G1D CHAPTER 30 ELECTRICAL SPECIFICATIONS 30.8.4 LVD circuit characteristics LVD Detection Voltage of Reset Mode and Interrupt Mode = –40 to +85°C, V ≤ V = AV ≤ 3.6 V, V = AV = 0 V) DD_RF DD_RF SS_RF SS_RF Parameter Symbol Conditions...
Page 889 RL78/G1D CHAPTER 30 ELECTRICAL SPECIFICATIONS LVD Detection Voltage of Interrupt & Reset Mode = –40 to +85°C, 1.6 V ≤ V = AV ≤ 3.6 V, V = AV = 0 V) DD_RF DD_RF SS_RF SS_RF Parameter Symbol Conditions MIN. TYP.
Page 890 RL78/G1D CHAPTER 30 ELECTRICAL SPECIFICATIONS 30.9 RF Transceiver Characteristics 30.9.1 RF transmission characteristics Unless specified otherwise, the measurement is performed by our evaluation board. = +25°C, V = AV = 3.0 V, f = 2440 MHz, V = AV = 0 V) DD_RF DD_RF SS_RF...
Page 891 RL78/G1D CHAPTER 30 ELECTRICAL SPECIFICATIONS 30.9.2 RF reception characteristics Unless specified otherwise, the measurement is performed by our evaluation board. = +25°C, V = AV = 3.0 V, f = 2440 MHz, V = AV = 0 V) DD_RF DD_RF SS_RF SS_RF Parameter...
Page 892 RL78/G1D CHAPTER 30 ELECTRICAL SPECIFICATIONS 30.9.3 Performance mapping for typical RF (Reference) (1) Peak Current during RF Transmission Unless specified otherwise, the measurement is performed by our evaluation board. Current consumption is not including MCU unit. = 3.0 V POWER = -1 dBm DD_RF = +25°C, DC-DC on R01UH0515EJ0120 Rev.1.20...
Page 893 RL78/G1D CHAPTER 30 ELECTRICAL SPECIFICATIONS = 3.0V, T = +25°C DD_RF (2) Peak Current during RF Reception Unless specified otherwise, the measurement is performed by our evaluation board. Current consumption is not including MCU unit. = 3.0 V DD_RF R01UH0515EJ0120 Rev.1.20 Dec 16, 2016...
Page 894 RL78/G1D CHAPTER 30 ELECTRICAL SPECIFICATIONS = +25°C (3) RF Output Power during Transmission Unless specified otherwise, the measurement is performed by our evaluation board. Current consumption is not including MCU unit. = 3.0V, f = 2402 MHz DD_RF R01UH0515EJ0120 Rev.1.20 Dec 16, 2016...
Page 895 RL78/G1D CHAPTER 30 ELECTRICAL SPECIFICATIONS = +25°C, f = 2402 MHz = 3.0V, T = +25°C DD_RF R01UH0515EJ0120 Rev.1.20 Dec 16, 2016...
Page 896 RL78/G1D CHAPTER 30 ELECTRICAL SPECIFICATIONS (4) RF Reception Sensitivity Unless specified otherwise, the measurement is performed by our evaluation board. Current consumption is not including MCU unit. = 3.0V, f = 2440 MHz DD_RF = +25°C, f = 2440 MHz R01UH0515EJ0120 Rev.1.20 Dec 16, 2016...
Page 897 2. When using flash memory programmer and Renesas Electronics self programming library 3. This shows the flash memory characteristics. This is a result obtained from Renesas Electronics reliability test. 30.12 Special Flash Memory Programming Communication (UART) = –40 to +85°C, 1.8 V ≤ V = AV ≤...
Page 898 RL78/G1D CHAPTER 30 ELECTRICAL SPECIFICATIONS 30.13 Timing of Entry to Flash Memory Programming Modes = –40 to +85°C, 1.8 V ≤ V = AV ≤ 3.6 V, V = AV = 0 V) DD_RF DD_RF SS_RF SS_RF Parameter Symbol Conditions MIN.
Page 899 Dimensions in millimeters Reference Symbol 5.90 6.00 6.10 5.90 6.00 6.10 0.80 0.00 0.15 0.20 0.25 0.40 0.20 0.30 0.40 0.05 0.05 0.80 S AB 0.80 0.20 4.73 4.73 © 2015 Renesas Electronics Corporation. All rights reserved. R01UH0515EJ0120 Rev.1.20 Dec 16, 2016...
Page 900 RL78/G1D APPENDIX A REVISION HISTORY APPENDIX A REVISION HISTORY A.1 Major Revisions in This Edition (1/1) Page Description Classification CHAPTER 1 OUTLINE Change of pin name in 1.3 Pin Configuration (Top View) CHAPTER 2 CONNECTION BETWEEN MCU AND RF TRANSCEIVER p.15 Change of Figure 2-3 Power Configuration p.15...
Page 901 RL78/G1D APPENDIX A REVISION HISTORY A.2 Revision History of Preceding Editions Here is the revision history of the preceding editions. Chapter indicates the chapter of each edition. (1/7) Edition Description Chapter Rev.1.10 Change of description in 1.1 Features CHAPTER 1 OUTLINE Change of 1.6 Outline of Functions Change of description in 2.1 Connection Pins of MCU and RF Transceiver CHAPTER 2...
Page 902 RL78/G1D APPENDIX A REVISION HISTORY (2/7) Edition Description Chapter Rev.1.10 Deletion of remark 2 in (7) Delay counter CHAPTER 7 TIMER ARRAY UNIT Deletion of remark 2 in Table 7-2. Timer I/O Pins provided in Each Product Change of notes of Figure 7-2. Internal Block Diagram of Channels 0, 2, 4, 6 of Timer Array Unit 0 Addition of remark to Figure 7-3.
Page 903 RL78/G1D APPENDIX A REVISION HISTORY (3/7) Edition Description Chapter Rev.1.10 Change of description in 12.6.2 Software trigger mode (one-shot conversion mode) CHAPTER 12 A/D CONVERTER Change of Figure 12-18. Example of Software Trigger Mode (One-Shot Conversion Mode) Operation Timing Addition of 12.6.3 Software trigger mode (scan mode, sequential conversion mode) Addition of 12.6.4 Software trigger mode (scan mode, one-shot conversion mode) Change of description in 12.6.5 Hardware trigger no-wait mode (sequential conversion mode)
Page 904 RL78/G1D APPENDIX A REVISION HISTORY (4/7) Edition Description Chapter Rev.1.10 Addition of note 2 to 13.1.1 3-wire serial I/O (CSI00, CSI20, CSI21) CHAPTER 13 SERIAL ARRAY UNIT Addition of Figure 13-2. Block Diagram of Serial Array Unit 1 Change of note 2 of 13.2.2 Lower 8/9 bits of the serial data register mn (SDRmn) Change of note 2 of Figure 13-8.
Page 905 RL78/G1D APPENDIX A REVISION HISTORY (5/7) Edition Description Chapter Rev.1.10 Change of caution and remark 1 of 13.6.4 Calculating baud rate CHAPTER 13 SERIAL ARRAY UNIT Change of Figure 13-97. Example of Contents of Registers for Address Field Transmission of Simplified I C (IIC00, IIC20) Deletion of remark in Figure 13-98.
Page 906 RL78/G1D APPENDIX A REVISION HISTORY (6/7) Edition Description Chapter Rev.1.10 Change of Table 19-1. Operating Statuses in HALT Mode CHAPTER 19 STANDBY FUNCTION Change of Table 19-3. Operating Statuses in SNOOZE Mode Deletion of caution in Figure 20-3. Timing of Reset Due to Watchdog Timer Overflow, CHAPTER 20 RESET FUNCTION Execution of Illegal Instruction, Detection of RAM Parity Error, or Detection of Illegal...
Page 907 RL78/G1D APPENDIX A REVISION HISTORY (7/7) Edition Description Chapter Rev.1.00 Change of description in 1.1 Features CHAPTER 1 OUTLINE Addition of description in 1.1 Features Change of Figure 1-1. Part Number, Memory Size, and Package of RL78/G1D Change of Table 1-1. List of Ordering Part Numbers Change of 1.3 Pin Configuration (Top View) Change of 1.4 Pin Identification Change of 1.5 Block Diagram...
Page 908 RL78/G1D User’s Manual: Hardware Publication Date: Rev.1.00 Apr 24, 2015 Rev.1.20 Dec 16, 2016 Published by: Renesas Electronics Corporation...
Page 909 SALES OFFICES SALES OFFICES http://www.renesas.com http://www.renesas.com Refer to "http://www.renesas.com/" for the latest and detailed information. Refer to "http://www.renesas.com/" for the latest and detailed information. Renesas Electronics America Inc. Renesas Electronics America Inc. 2801 Scott Boulevard Santa Clara, CA 95050-2549, U.S.A.
Page 910 RL78/G1D R01UH0515EJ0120...

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