Renesas RL78 Series User Manual page 490

RL78/G1D
(1) Register setting
Figure 13-75. Example of Contents of Registers for UART Transmission of UART
(a) Serial mode register mn (SMRmn)
15 14
SMRmn
CKSmn CCSmn
0/1 0
Operation clock (f
0: Prescaler output clock CKm0 set by the SPSm register
1: Prescaler output clock CKm1 set by the SPSm register
(b) Serial communication operation setting register mn (SCRmn)
15 14
SCRmn
TXEmn RXEmn
1 0
Setting of parity bit
00B: No parity
01B: Appending 0 parity
10B: Appending Even parity
11B: Appending Odd parity
(c) Serial data register mn (SDRmn) (lower 8 bits: TXDq)
15 14
SDRmn
(d) Serial output level register 0 (SOL0) ... Sets only the bits of the target channel.
15 14
SOL0
0 0
Notes 1. Only provided for the SCR00 register. This bit is fixed to 1 for the other registers.
2. When UART0 performs 9-bit communication, bits 0 to 8 of the SDRm0 register are used as the
transmission data specification area. Only UART0 can be specified for the 9-bit data length.
Remarks 1. m: Unit number (m = 0), n: Channel number (n = 0, 2), q: UART number (q = 0, 1),
mn = 00, 02
2. : Setting is fixed in the UART transmission mode,
×: Bit that cannot be used in this mode (set to the initial value when not used in any mode)
0/1: Set to 0 or 1 depending on the usage of the user
R01UH0515EJ0120 Rev.1.20
Dec 16, 2016
(UART0, UART1) (1/2)
13 12 11 10
0 0 0 0
) of channel n
MCK
13 12 11 10
DAPmn CKPmn EOCmn PTCmn1
0 0 0 0
Selection of data transfer sequence
0: Inputs/outputs data with MSB first
1: Inputs/outputs data with LSB first.
13 12 11 10
Baud rate setting
13 12 11 10
0 0 0 0
9 8 7 6
0 0 0 0
9 8 7 6
PTCmn0 DIRmn SLCmn1
0/1 0/1 0/1 0 0/1
9 8 7 6
Note
0
9 8 7 6
0 0 0 0
0: Non-reverse (normal) transmission
1: Reverse transmission
: Setting disabled (set to the initial value)
CHAPTER 13 SERIAL ARRAY UNIT
5 4 3 2 1
MDmn2 MDmn1
1 0 0 0 1
Interrupt source of channel n
0: Transfer end interrupt
1: Buffer empty interrupt
5 4 3 2 1
SLCmn0 DLSmn1
0/1 0 1 0/1
Note
Setting of stop bit
01B: Appending 1 bit
10B: Appending 2 bits
5 4 3 2 1
Transmit data setting
TXDq
5 4 3 2 1
SOLm2
0 0 0 0/1 0
0
MDmn0
0/1
0
DLSmn0
0/1
0
0
SOLm0
0/1
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