Example Of Setting X1 Oscillation Clock - Renesas RL78/G1P Hardware User Manual

16-bit single-chip microcontroller
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RL78/G1P

5.6.2 Example of setting X1 oscillation clock

After a reset release, the CPU/peripheral hardware clock (f
oscillator clock. To subsequently change the clock to the X1 oscillation clock, set the oscillator and start oscillation by
using the oscillation stabilization time select register (OSTS) and clock operation mode control register (CMC) and clock
operation status control register (CSC) and wait for oscillation to stabilize by using the oscillation stabilization time counter
status register (OSTC). After the oscillation stabilizes, set the X1 oscillation clock to f
register (CKC).
[Register settings] Set the register in the order of <1> to <5> below.
<1> Set (1) the OSCSEL bit of the CMC register, except for the cases where f
AMPH bit, to operate the X1 oscillator.
7
EXCLK
CMC
0
Note Set AMPH bit to 0 when X1 clock is 10 MHz or below.
<2> Using the OSTS register, select the oscillation stabilization time of the X1 oscillator at releasing of the STOP mode.
Example: Setting values when a wait of at least 102
7
OSTS
0
<3> Clear (0) the MSTOP bit of the CSC register to start oscillating the X1 oscillator.
7
MSTOP
CSC
0
<4> Use the OSTC register to wait for oscillation of the X1 oscillator to stabilize.
Example: Wait until the bits reach the following values when a wait of at least 102
resonator.
7
MOST8
OSTC
1
<5> Use the MCM0 bit of the CKC register to specify the X1 oscillation clock as the CPU/peripheral hardware clock.
7
CKC
0
R01UH0895EJ0100 Rev.1.00
Nov 29, 2019
6
5
OSCSEL
1
0
6
5
0
0
6
5
1
0
6
5
MOST9
MOST10
MOST11
1
1
6
5
MCS
MCM0
0
0
CHAPTER 5 CLOCK GENERATOR
) always starts operating with the high-speed on-chip
CLK
X
4
3
2
0
0
0
s is set based on a 10 MHz resonator.
4
3
2
OSTS2
0
0
0
4
3
2
0
0
0
4
3
2
MOST13
MOST15
0
0
0
4
3
2
1
0
0
by using the system clock control
CLK
> 10 MHz, in such cases set (1) the
1
0
AMPH
0
0/1
1
0
OSTS1
OSTS0
1
0
1
0
HIOSTOP
0
0
s is set based on a 10 MHz
1
0
MOST17
MOST18
0
0
1
0
0
0
Note
118

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