Renesas RL78 Series User Manual page 819

RL78/G1D
Instruction
Mnemonic
Group
8-bit data MOV A, [HL+B]
transfer
[HL+B], A
A, ES:[HL+B]
ES:[HL+B], A
A, [HL+C]
[HL+C], A
A, ES:[HL+C]
ES:[HL+C], A
X, !addr16
X, ES:!addr16
X, saddr
B, !addr16
B, ES:!addr16
B, saddr
C, !addr16
C, saddr
ES, saddr
XCH A, r
A, !addr16
A, ES:!addr16
A, saddr
A, sfr
A, [DE]
A, ES:[DE]
A, [HL]
A, ES:[HL]
A, [DE+byte]
A, ES:[DE+byte]
A, [HL+byte]
A, ES:[HL+byte]
Notes 1. Number of CPU clocks (f
when no data is accessed.
2. Number of CPU clocks (f
accessed by an 8-bit instruction.
3. Except r = A
Remark Number of clock is when program exists in the internal ROM (flash memory) area. If fetching the instruction
from the internal RAM area, the number becomes double number plus 3 clocks at a maximum.
R01UH0515EJ0120 Rev.1.20
Dec 16, 2016
Table 29-5. Operation List (3/17)
Operands Bytes
Note 1 Note 2
2
2
3
3
2
2
3
3
3
4
2
3
4
2
3
2
3
Note 3
1 (r = X)
2 (other
than r =
X)
4
5
3
3
2
3
2
3
3
4
3
4
) when the internal RAM area, SFR area, or extended SFR area is accessed, or
CLK
) when the code flash memory is accessed, or when the data flash memory is
CLK
Clocks
1 4 A ← (HL + B)
1 – (HL + B) ← A
2 5 A ← ((ES, HL) + B)
2 – ((ES, HL) + B) ← A
1 4 A ← (HL + C)
1 – (HL + C) ← A
2 5 A ← ((ES, HL) + C)
2 – ((ES, HL) + C) ← A
1 4 X ← (addr16)
2 5 X ← (ES, addr16)
1 – X ← (saddr)
1 4 B ← (addr16)
2 5 B ← (ES, addr16)
1 – B ← (saddr)
1 4 C ← (addr16)
1 – C ← (saddr)
1 – ES ← (saddr)
1 – A ←→ r
2 – A ←→ (addr16)
3 – A ←→ (ES, addr16)
2 – A ←→ (saddr)
2 – A ←→ sfr
2 – A ←→ (DE)
3 – A ←→ (ES, DE)
2 – A ←→ (HL)
3 – A ←→ (ES, HL)
2 – A ←→ (DE + byte)
3 – A ←→ ((ES, DE) + byte)
2 – A ←→ (HL + byte)
3 – A ←→ ((ES, HL) + byte)
CHAPTER 29 INSTRUCTION SET
Operation Flag
Z AC CY
798