Renesas RL78 Series User Manual page 484

RL78/G1D
13.5.8 Calculating transfer clock frequency
The transfer clock frequency for 3-wire serial I/O (CSI00, CSI20, CSI21) communication can be calculated by the
following expressions.
(1) Master
(Transfer clock frequency) = {Operation clock (f
(2) Slave
(Transfer clock frequency) = {Frequency of serial clock (SCK) supplied by master}
Note The permissible maximum transfer clock frequency is f
Remark The value of SDRmn[15:9] is the value of bits 15 to 9 of serial data register mn (SDRmn) (0000000B to
1111111B) and therefore is 0 to 127.
The operation clock (f
MCK
register mn (SMRmn).
R01UH0515EJ0120 Rev.1.20
Dec 16, 2016
MCK
) is determined by serial clock select register m (SPSm) and bit 15 (CKSmn) of serial mode
CHAPTER 13 SERIAL ARRAY UNIT
) frequency of target channel} ÷ (SDRmn[15:9] + 1)
/6.
MCK
÷
2 [Hz]
Note
[Hz]
463