Renesas RL78 Series User Manual page 405

RL78/G1D
Address: FFF10H, FFF11H (SDR00), FFF12H, FFF13H (SDR01)
Symbol 15 14
SDRmn
Address: FFF44H, FFF45H (SDR02), FFF46H, FFF47H (SDR03),
FFF48H, FFF49H (SDR10), FFF4AH, FFF4BH (SDR11)
Symbol 15 14
SDRmn
0 0
0 0
0 0
0 0
● ●
● ●
● ●
1 1
1 1
Cautions 1. Be sure to clear bit 8 of the SDR02, SDR03, SDR10, and SDR11 to "0".
2. Setting SDRmn[15:9] = (0000000B, 0000001B) is prohibited when UART is used.
3. Setting SDRmn[15:9] = 0000000B is prohibited when simplified I
to 0000001B or greater.
4. When operation is stopped (SEmn = 0), do not rewrite SDRmn[7:0] by an 8-bit memory
manipulation instruction (SDRmn[15:9] are all cleared to 0).
Remarks 1. For the function of the lower 8/9 bits of the SDRmn register, see 13.2 Configuration of Serial
Array Unit.
2. m: Unit number (m = 0, 1), n: Channel number (n = 0 to 3 for m = 0, n = 0, 1 for m = 1)
R01UH0515EJ0120 Rev.1.20
Dec 16, 2016
Figure 13-9. Format of Serial Data Register mn (SDRmn)
FFF11H (SDR00)
13 12 11 10
FFF45H (SDR02)
13 12 11 10
SDRmn[15:9]
0 0 0 0
0 0 0 0
0 0 0 1
0 0 0 1
● ● ● ●
● ● ● ●
● ● ● ●
1 1 1 1
1 1 1 1
CHAPTER 13 SERIAL ARRAY UNIT
After reset: 0000H
9 8 7 6
0
After reset: 0000H
9 8 7 6
0
Transfer clock setting by dividing the operating clock
0
1
0
1
●
●
●
0
1
R/W
FFF10H (SDR00)
5 4 3 2
R/W
FFF44H (SDR02)
5 4 3 2
f /2
MCK
f /4
MCK
f /6
MCK
f /8
MCK
●
●
●
f /254
MCK
f /256
MCK
2
C is used. Set SDRmn[15:9]
1 0
1 0
384