Renesas RL78 Series User Manual page 618

RL78/G1D
(9-Clock Wait Is Selected for Master, 9-Clock Wait Is Selected for Slave) (4/4)
Master side
IICAn
ACKDn
(ACK detection)
WTIMn
(8 or 9 clock wait)
ACKEn
(ACK control)
MSTSn
(communication status)
STTn
(ST trigger)
SPTn
(SP trigger)
WRELn
(wait cancellation)
INTIICAn
(interrupt)
TRCn
(transmit/receive)
Bus line
SCLAn (bus)
(clock line)
SDAAn (bus)
(data line)
Slave side
IICAn
ACKDn
(ACK detection)
STDn
(ST detection)
SPDn
(SP detection)
WTIMn
(8 or 9 clock wait)
ACKEn
(ACK control)
MSTSn
(communication status)
WRELn
(wait cancellation)
INTIICAn
(interrupt)
TRCn
(transmit/receive)
: Wait state by master device
Notes 1. Make sure that the time between the rise of the SCLAn pin signal and the generation of the start
condition after a restart condition has been issued is at least 4.7 µs when specifying standard mode and
at least 0.6 µs when specifying fast mode.
2. For releasing wait state during reception of a slave device, write "FFH" to IICAn or set the WRELn bit.
Remark n = 0
R01UH0515EJ0120 Rev.1.20
Dec 16, 2016
Figure 14-32. Example of Master to Slave Communication
(d) Data ~ restart condition ~ address
H
H
H
L
L
H
ACK
D 3 D 2 D 1 D 0
1 1 1 1
<7>
L
H
H
L
L
: Wait state by slave device
CHAPTER 14 SERIAL INTERFACE IICA
<iii>
<ii>
<8>
Note 1
<i> Note 2
Restart condition
AD5 AD4 AD3 AD2
AD6
Slave address
: Wait state by master and slave devices
AD1
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