Renesas RL78 Series User Manual page 832

RL78/G1D
Instruction Mnemon
Group ic
Stack PUSH PSW
manipulate
rp
POP PSW
rp
MOVW SP, #word
SP, AX
AX, SP
HL, SP
BC, SP
DE, SP
ADDW SP, #byte
SUBW SP, #byte
Unconditio BR AX
nal branch
$addr20
$!addr20
!addr16
!!addr20
Conditional
BC $addr20
branch
BNC $addr20
BZ $addr20
BNZ $addr20
BH $addr20
BNH $addr20
BT saddr.bit, $addr20
sfr.bit, $addr20
A.bit, $addr20
PSW.bit, $addr20
[HL].bit, $addr20
ES:[HL].bit,
$addr20
Notes 1. Number of CPU clocks (f
when no data is accessed.
2. Number of CPU clocks (f
accessed by an 8-bit instruction.
3. This indicates the number of clocks "when condition is not met/when condition is met".
Remark Number of clock is when program exists in the internal ROM (flash memory) area. If fetching the instruction
from the internal RAM area, the number becomes double number plus 3 clocks at a maximum.
R01UH0515EJ0120 Rev.1.20
Dec 16, 2016
Table 29-5. Operation List (16/17)
Operands Bytes
Note 1 Note 2
2
1
2
1
4
2
2
3
3
3
2
2
2
2
3
3
4
2 2/4
2 2/4
2 2/4
2 2/4
3 2/4
3 2/4
4 3/5
4 3/5
3 3/5
4 3/5
3 3/5
4 4/6
) when the internal RAM area, SFR area, or extended SFR area is accessed, or
CLK
) when the code flash memory is accessed, or when the data flash memory is
CLK
Clocks
1 – (SP – 1) ← PSW, (SP – 2) ← 00H
1 – (SP – 1) ← rp
SP ← SP – 2
3 – PSW ← (SP+1), SP ← SP + 2
1 – rp ←(SP), rp
L
1 – SP ← word
1 – SP ← AX
1 – AX ← SP
1 – HL ← SP
1 – BC ← SP
1 – DE ← SP
1 – SP ← SP + byte
1 – SP ← SP – byte
3 – PC ← CS, AX
3 – PC ← PC + 2 + jdisp8
3 – PC ← PC + 3 + jdisp16
3 – PC ← 0000, addr16
3 – PC ← addr20
Note3
– PC ← PC + 2 + jdisp8 if CY = 1
Note3
– PC ← PC + 2 + jdisp8 if CY = 0
Note3
– PC ← PC + 2 + jdisp8 if Z = 1
Note3
– PC ← PC + 2 + jdisp8 if Z = 0
Note3
– PC ← PC + 3 + jdisp8 if (Z⋁ CY)=0
Note3
– PC ← PC + 3 + jdisp8 if (Z⋁ CY)=1
Note3
– PC ← PC + 4 + jdisp8 if (saddr).bit = 1
Note3
– PC ← PC + 4 + jdisp8 if sfr.bit = 1
Note3
– PC ← PC + 3 + jdisp8 if A.bit = 1
Note3
– PC ← PC + 4 + jdisp8 if PSW.bit = 1
Note3
6/7 PC ← PC + 3 + jdisp8 if (HL).bit = 1
Note3
7/8 PC ← PC + 4 + jdisp8
CHAPTER 29 INSTRUCTION SET
Operation
, (SP – 2) ← rp ,
H L
← (SP+1), SP ← SP + 2
H
Flag
Z AC CY
R R R
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