RL78/G1D
Figure 7-49. Example of Basic Timing of Operation as Frequency Divider (MD000 = 1)
TCR00
TDR00
INTTM00
Remark TS00:
R01UH0515EJ0120 Rev.1.20
Dec 16, 2016
TS00
TE00
TI00
2
1
0
0000H
0002H
TO00
Divided
by 6
Bit n of timer channel start register 0 (TS0)
TE00:
Bit n of timer channel enable status register 0 (TE0)
TI00:
TI00 pin input signal
TCR00: Timer count register 00 (TCR00)
TDR00: Timer data register 00 (TDR00)
TO00:
TO00 pin output signal
2
2
1
1
1
0
0
0
CHAPTER 7 TIMER ARRAY UNIT
1
1
1
0
0
0
0001H
Divided
by 4
224