Renesas RL78 Series User Manual page 693

RL78/G1D
Figure 18-2. Format of Interrupt Request Flag Registers (IF0L, IF0H, IF1L, IF1H, IF2L, IF2H, IF3L) (2/2)
Address: FFFD1H
Symbol <7>
IF2H FLIF
Address: FFFD2H
Symbol 7
IF3L 0
XXIFX
0
1
Cautions 1. Be sure to set bits that are not available to the initial value.
2. When manipulating a flag of the interrupt request flag register, use a 1-bit memory
manipulation instruction (CLR1). When describing in C language, use a bit manipulation
instruction such as "IF0L.0 = 0;" or "_asm("clr1 IF0L, 0");" because the compiled assembler
must be a 1-bit memory manipulation instruction (CLR1).
If a program is described in C language using an 8-bit memory manipulation instruction
such as "IF0L &= 0xfe;" and compiled, it becomes the assembler of three instructions.
mov a, IF0L
and a, #0FEH
mov IF0L, a
In this case, even if the request flag of the another bit of the same interrupt request flag
register (IF0L) is set to 1 at the timing between "mov a, IF0L" and "mov IF0L, a", the flag is
cleared to 0 at "mov IF0L, a". Therefore, care must be exercised when using an 8-bit
memory manipulation instruction in C language.
R01UH0515EJ0120 Rev.1.20
Dec 16, 2016
After reset: 00H R/W
6 <5>
0 MDIF
After reset: 00H R/W
6 5
0 0
No interrupt request signal is generated
Interrupt request is generated, interrupt request status
CHAPTER 18 INTERRUPT FUNCTIONS
4 3 2
0 0 0
4 3 2
0 0 0
Interrupt request flag
1 <0>
0 PIF11
<1> <0>
DMAIF3 DMAIF2
672