Renesas RL78 Series User Manual page 350

RL78/G1D
Figure 12-7. Format of A/D Converter Mode Register 2 (ADM2) (2/2)
Address: F0010H After reset: 00H
Symbol 7
ADM2 ADREFP1
ADRCK
0
1
Figure 12-8 shows the generation range of the interrupt signal (INTAD) for AREA 1 to AREA 3.
AWC
0
1
When there is a hardware trigger signal in the STOP mode, the STOP mode is exited, and A/D conversion is performed
without operating the CPU (the SNOOZE mode).
● The SNOOZE mode function can only be specified when the high-speed on-chip oscillator clock is selected for the
CPU/peripheral hardware clock (f
● Using the SNOOZE mode function in the software trigger mode or hardware trigger no-wait mode is prohibited.
● Using the SNOOZE mode function in the sequential conversion mode is prohibited.
● When using the SNOOZE mode function, specify a hardware trigger interval of at least "shift time to SNOOZE
Note
mode + conversion start time + A/D power supply stabilization wait time + A/D conversion time +2 f
● Even when using SNOOZE mode, be sure to set the AWC bit to 0 in normal operation mode and change it to 1 just
before shifting to STOP mode.
Also, be sure to change the AWC bit to 0 after returning from STOP mode to normal operation mode.
If the AWC bit is left set to 1, A/D conversion will not start normally in spite of the subsequent SNOOZE or normal
operation mode.
ADTYP
0
1
Note Refer to "Transition time from STOP mode to SNOOZE mode" in 19.3.3 SNOOZE mode
Caution Only rewrite the value of the ADM2 register while conversion operation is stopped (ADCS = 0, ADCE
= 0).
R01UH0515EJ0120 Rev.1.20
Dec 16, 2016
R/W
6 5
ADREFP0 ADREFM
Checking the upper limit and lower limit conversion result values
The interrupt signal (INTAD) is output when the ADLL register ≤ the ADCR register ≤ the ADUL register
(AREA 1).
The interrupt signal (INTAD) is output when the ADCR register < the ADLL register (AREA 2) or the
ADUL register < the ADCR register (AREA 3).
Do not use the SNOOZE mode function.
Use the SNOOZE mode function.
). If any other clock is selected, specifying this mode is prohibited.
CLK
10-bit resolution
8-bit resolution
4
<3>
0 ADRCK
Specification of the SNOOZE mode
Selection of the A/D conversion resolution
CHAPTER 12 A/D CONVERTER
<2> 1
AWC 0
clock"
CLK
<0>
ADTYP
329