Renesas RL78 Series User Manual page 831

RL78/G1D
Instruction
Mnemonic
Group
Call/ CALL rp
return
$!addr20
!addr16
!!addr20
CALLT
[addr5]
BRK
RET
RETI
RETB
Notes 1. Number of CPU clocks (f
when no data is accessed.
2. Number of CPU clocks (f
accessed by an 8-bit instruction.
Remark Number of clock is when program exists in the internal ROM (flash memory) area. If fetching the instruction
from the internal RAM area, the number becomes double number plus 3 clocks at a maximum.
R01UH0515EJ0120 Rev.1.20
Dec 16, 2016
Table 29-5. Operation List (15/17)
Operands Bytes
Note 1 Note 2
2
3
3
4
2
–
- 1
- 2
- 2
) when the internal RAM area, SFR area, or extended SFR area is accessed, or
CLK
) when the code flash memory is accessed, or when the data flash memory is
CLK
Clocks
3 – (SP – 2) ← (PC+2)
(SP – 4) ← (PC+2)
SP ← SP – 4
3 – (SP – 2) ← (PC+3)
(SP – 4) ← (PC+3)
SP ← SP – 4
3 – (SP – 2) ← (PC+3)
(SP – 4) ← (PC+3)
SP ← SP – 4
(SP – 2) ← (PC+4)
3 –
(SP – 4) ← (PC+4)
SP ← SP – 4
5 – (SP – 2) ← (PC+2)
(SP – 4) ← (PC+2)
PC ← (0000, addr5+1),
H
PC ← (0000, addr5),
L
SP ← SP – 4
2 5 (SP – 1) ← PSW, (SP – 2) ← (PC+2)
(SP – 3) ← (PC+2)
PC ← 0000,
S
PC ← (0007FH), PC
H
SP ← SP – 4, IE ← 0
6 – PC ← (SP), PC
L
PC ← (SP+2), SP ← SP+4
S
6 – PC ← (SP), PC
L
PC ← (SP+2), PSW← (SP+3),
S
SP ← SP+4
6 – PC ← (SP), PC
L
PC ← (SP+2), PSW ← (SP+3),
S
SP ← SP+4
CHAPTER 29 INSTRUCTION SET
Operation
, (SP – 3) ← (PC+2) ,
S H
, PC ← CS, rp,
L
, (SP – 3) ← (PC+3) ,
S H
, PC ← PC+3+jdisp16,
L
, (SP – 3) ← (PC+3) ,
S H
, PC ← 0000, addr16,
L
, (SP – 3) ← (PC+4) ,
S H
, PC ← addr20,
L
, (SP – 3) ← (PC+2) ,
S H
, PC ← 0000,
L S
,
S
, (SP – 4) ← (PC+2) ,
H L
← (0007EH),
L
← (SP+1),
H
← (SP+1),
H
← (SP+1),
H
Flag
Z AC CY
R R R
R R R
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