Renesas RL78 Series User Manual page 558

RL78/G1D
CLDn
0
1
Condition for clearing (CLDn = 0)
● When the SCLAn pin is at low level
● When IICEn = 0 (operation stop)
● Reset
DADn
0
1
Condition for clearing (DADn = 0)
● When the SDAAn pin is at low level
● When IICEn = 0 (operation stop)
● Reset
SMCn
0
1
DFCn
0
1
Use the digital filter only in fast mode and fast mode plus.
The digital filter is used for noise elimination.
The transfer clock does not vary, regardless of the DFCn bit being set (1) or cleared (0).
PRSn
0
1
Cautions1.
2.
Remarks 1.
R01UH0515EJ0120 Rev.1.20
Dec 16, 2016
Figure 14-9. Format of IICA Control Register n1 (IICCTLn1) (2/2)
Detection of SCLAn pin level (valid only when IICEn = 1)
The SCLAn pin was detected at low level.
The SCLAn pin was detected at high level.
Detection of SDAAn pin level (valid only when IICEn = 1)
The SDAAn pin was detected at low level.
The SDAAn pin was detected at high level.
Operates in standard mode (fastest transfer rate: 100 kbps).
Operates in fast mode (fastest transfer rate: 400 kbps) or fast mode plus (fastest transfer rate: 1
Mbps).
Digital filter off.
Digital filter on.
Selects f (1 MHz ≤ f ≤ 20 MHz).
CLK
CLK
Selects f /2 (20 MHz < f
CLK
CLK
The fastest operation frequency of the IICA operation clock (f
Set bit 0 (PRSn) of the IICA control register n1 (IICCTLn1) to "1" only when the f
exceeds 20 MHz.
Note the minimum f
minimum f operation frequency for serial interface IICA is determined according
CLK
to the mode.
Fast mode: f = 3.5 MHz (min.)
CLK
Fast mode plus: f
CLK
Normal mode: f = 1 MHz (min.)
CLK
IICEn: Bit 7 of IICA control register n0 (IICCTLn0)
2. n = 0
CHAPTER 14 SERIAL INTERFACE IICA
Condition for setting (CLDn = 1)
● When the SCLAn pin is at high level
Condition for setting (DADn = 1)
● When the SDAAn pin is at high level
Operation mode switching
Digital filter operation control
IICA operation clock (f
MCK
).
operation frequency when setting the transfer clock. The
CLK
= 10 MHz (min.)
) control
) is 20 MHz (max.).
MCK
CLK
537