Renesas RL78 Series User Manual page 674

RL78/G1D
17.5.2 Consecutive capturing of A/D conversion results
A flowchart of an example of setting for consecutively capturing A/D conversion results is shown below.
● Consecutive capturing of A/D conversion results.
● DMA channel 1 is used for DMA transfer.
● DMA start source: INTAD
● Interrupt of A/D is specified by IFC13 to IFC10 = 0001B.
● Transfers FFF1EH and FFF1FH (2 bytes) of the 10-bit A/D conversion result register (ADCR) to 512 bytes of
FFCE0H to FFEDFH of RAM.
Remark IFC13 to IFC10: Bits 3 to 0 of DMA mode control registers 1 (DMC1)
R01UH0515EJ0120 Rev.1.20
Dec 16, 2016
CHAPTER 17 DMA CONTROLLER
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