Renesas RL78 Series User Manual page 17

17.1 Functions of DMA Controller .................................................................................................. 640
17.2 Configuration of DMA Controller ............................................................................................ 641
17.2.1 DMA SFR address register n (DSAn) ........................................................................................... 641
17.2.2 DMA RAM address register n (DRAn) .......................................................................................... 642
17.2.3 DMA byte count register n (DBCn) ............................................................................................... 643
17.3 Registers Controlling DMA Controller ................................................................................... 644
17.3.1 DMA mode control register n (DMCn) .......................................................................................... 645
17.3.2 DMA operation control register n (DRCn) ..................................................................................... 648
17.4 Operation of DMA Controller ................................................................................................... 649
17.4.1 Operation procedure .................................................................................................................... 649
17.4.2 Transfer mode .............................................................................................................................. 650
17.4.3 Termination of DMA transfer ........................................................................................................ 650
17.5 Example of Setting of DMA Controller ................................................................................... 651
17.5.1 CSI consecutive transmission ...................................................................................................... 651
17.5.2 Consecutive capturing of A/D conversion results ......................................................................... 653
17.5.3 UART consecutive reception + ACK transmission........................................................................ 655
17.5.4 Holding DMA transfer pending by DWAITn bit ............................................................................. 657
17.5.5 Forced termination by software .................................................................................................... 658
17.6 Cautions on Using DMA Controller ........................................................................................ 660
CHAPTER 18 INTERRUPT FUNCTIONS ............................................................................................. 663
18.1 Interrupt Function Types ......................................................................................................... 663
18.2 Interrupt Sources and Configuration ..................................................................................... 664
18.3 Registers Controlling Interrupt Functions ............................................................................. 669
18.3.1 Interrupt request flag registers (IF0L, IF0H, IF1L, IF1H, IF2L, IF2H, IF3L) .................................. 671
18.3.2 Interrupt mask flag registers (MK0L, MK0H, MK1L, MK1H, MK2L, MK2H, MK3L) ....................... 673
18.3.3 Priority specification flag registers (PR00L, PR00H, PR01L, PR01H, PR02L, PR02H,
PR03L, PR10L, PR10H, PR11L, PR11H, PR12L, PR12H, PR13L) ............................................. 675
18.3.4 External interrupt rising edge enable registers (EGP0),
external interrupt falling edge enable registers (EGN0) ................................................................. 678
18.3.5 Program status word (PSW) ......................................................................................................... 679
18.4 Interrupt Servicing Operations ............................................................................................... 680
18.4.1 Maskable interrupt request acknowledgment ............................................................................... 680
18.4.2 Software interrupt request acknowledgment ................................................................................ 683
18.4.3 Multiple interrupt servicing ............................................................................................................ 683
18.4.4 Interrupt request hold ................................................................................................................... 687
CHAPTER 19 STANDBY FUNCTION .................................................................................................. 688
19.1 Standby Function ..................................................................................................................... 688
19.2 Registers Controlling Standby Function ............................................................................... 689
19.3 Standby Function Operation ................................................................................................... 689
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