Renesas RL78 Series User Manual page 225

RL78/G1D
(2) Default level of TO0n pin and output level after timer operation start
The change in the output level of the TO0n pin when timer output register 0 (TO0) is written while timer output is
disabled (TOE0n = 0), the initial level is changed, and then timer output is enabled (TOE0n = 1) before port output
is enabled, is shown below.
(a) When operation starts with master channel output mode (TOM0n = 0) setting
The setting of timer output level register m (TOL0) is invalid when master channel output mode (TOM0n = 0).
When the timer operation starts after setting the default level, the toggle signal is generated and the output
level of the TO0n pin is reversed.
0n
TOE
Default
-
Hi Z
status
n
TO0
(output)
Port output is enabled
Remarks 1. Toggle: Reverse TO0n pin output status
2. n: Channel number (n = 0 to 7)
R01UH0515EJ0120 Rev.1.20
Dec 16, 2016
Figure 7-31. TO0n Pin Output Status at Toggle Output (TOM0n = 0)
Toggle Toggle Toggle
CHAPTER 7 TIMER ARRAY UNIT
TO0n bit = 0
(Default status : Low)
TO0n bit = 1
(Default status : High)
TO0n bit = 0
(Default status : Low)
TO0n bit = 1
(Default status : High)
Bold : Active level
Toggle Toggle
TO0n bit = 0
(Active high)
TO0n bit = 1
(Active low)
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