Renesas RL78 Series User Manual page 747

RL78/G1D
22.4.3 When used as interrupt & reset mode
Specify the operation mode (the interrupt & reset (LVIMDS1, LVIMDS0 = 1, 0)) and the detection voltage (V
by using the option byte 000C1H.
The operation is started in the following initial setting state when the interrupt & reset mode is set.
● Bit 7 (LVISEN) of the voltage detection register (LVIM) is set to 0 (disable rewriting of voltage detection level
register (LVIS))
● The initial value of the voltage detection level select register (LVIS) is set to 00H.
Bit 7 (LVIMD) is 0 (interrupt mode).
Bit 0 (LVILV) is 0 (high-voltage detection level: V
● Operation in LVD interrupt & reset mode
In the interrupt & reset mode (option byte LVIMDS1, LVIMDS0 = 1, 0), the state of an internal reset by LVD is
retained until the supply voltage (V
The internal reset is released when the supply voltage (V
An interrupt request signal by LVD (INTLVI) is generated and arbitrary save processing is performed when the
supply voltage (V
generated when the supply voltage (V
generated, an interrupt request signal is not generated even if the supply voltage becomes equal to or higher than
the high-voltage detection voltage (V
To use the LVD reset & interrupt mode, perform the processing according to Figure 22-8 Processing Procedure
After an Interrupt Is Generated and Figure 22-setting9 Initial Setting of Interrupt and Reset Mode.
Figure 22-7 shows the timing of the internal reset signal and interrupt signal generated in the LVD interrupt & reset
mode.
R01UH0515EJ0120 Rev.1.20
Dec 16, 2016
) exceeds the high-voltage detection level (V
DD
) falls below the high-voltage detection level (V
DD
) falls below the low-voltage detection level (V
DD
) without falling below the low-voltage detection voltage (V
LVDH
CHAPTER 22 VOLTAGE DETECTOR
).
LVDH
) exceeds the high-voltage detection level (V
DD
). After that, an internal reset by LVD is
LVDH
, V
LVDH LVDL
) after power is supplied.
LVDH
).
LVDH
). After INTLVD is
LVDL
).
LVDL
)
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