Renesas RL78 Series User Manual page 499

RL78/G1D
13.6.2 UART reception
UART reception is an operation wherein the RL78 microcontroller asynchronously receives data from another device
(start-stop synchronization).
For UART reception, the odd-number channel of the two channels used for UART is used. The SMR register of both
the odd- and even-numbered channels must be set.
UART
Target channel
Pins used
Interrupt
Error interrupt
Error detection flag
Transfer data length
Note 2
Transfer rate
Data phase
Parity bit
Stop bit
Data direction
Notes 1. Only UART0 can be specified for the 9-bit data length.
2. Use this operation within a range that satisfies the conditions above and the peripheral functions
characteristics in the electrical specifications (see CHAPTER 30 ELECTRICAL SPECIFICATIONS).
Remarks 1. f : Operation clock frequency of target channel
MCK
f : System clock frequency
CLK
2. m: Unit number (m = 0), n: Channel number (n = 1, 3), mn = 01, 03
R01UH0515EJ0120 Rev.1.20
Dec 16, 2016
UART0
Channel 1 of SAU0
RxD0
INTSR0
Transfer end interrupt only (Setting the buffer empty interrupt is prohibited.)
INTSRE0 INTSRE1
● Framing error detection flag (FEFmn)
● Parity error detection flag (PEFmn)
● Overrun error detection flag (OVFmn)
Note 1
7, 8 or 9 bits
Max. f /6 [bps] (SDRmn [15:9] = 2 or more), Min. f
MCK
Non-reverse output (default: high level)
Reverse output (default: low level)
The following selectable
● No parity bit (no parity check)
● No parity judgment (0 parity)
● Even parity check
● Odd parity check
Appending 1 bit
MSB or LSB first
CHAPTER 13 SERIAL ARRAY UNIT
UART1
Channel 3 of SAU0
RxD1
INTSR1
INTSRE2 INTSRE3
15
/(2 × 2 × 128) [bps]
CLK
478