Renesas RL78 Series User Manual page 564

RL78/G1D
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14.5 I C Bus Definitions and Control Methods
The following section describes the I
Figure 14-14 shows the transfer timing for the "start condition", "address", "data", and "stop condition" output via the I
bus's serial data bus.
SCLAn
SDAAn
Start
condition
The master device generates the start condition, slave address, and stop condition.
The acknowledge (ACK) can be generated by either the master or slave device (normally, it is output by the device that
receives 8-bit data).
The serial clock (SCLAn) is continuously output by the master device. However, in the slave device, the SCLAn pin low
level period can be extended and a wait can be inserted.
14.5.1 Start conditions
A start condition is met when the SCLAn pin is at high level and the SDAAn pin changes from high level to low level.
The start conditions for the SCLAn pin and SDAAn pin are signals that the master device generates to the slave device
when starting a serial transfer. When the device is used as a slave, start conditions can be detected.
A start condition is output when bit 1 (STTn) of IICA control register n0 (IICCTLn0) is set (1) after a stop condition has
been detected (SPDn: Bit 0 of the IICA status register n (IICSn) = 1). When a start condition is detected, bit 1 (STDn) of
the IICSn register is set (1).
Remark n = 0
R01UH0515EJ0120 Rev.1.20
Dec 16, 2016
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C bus's serial data communication format and the signals used by the I
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Figure 14-14. I C Bus Serial Data Transfer Timing
1-7 8 9
Address R/W ACK
Figure 14-15. Start Conditions
H
SCLAn
SDAAn
CHAPTER 14 SERIAL INTERFACE IICA
1-8 9 1-8
Data ACK Data
9
ACK Stop
condition
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C bus.
2
C
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